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US 6,647,475 B2Granted
Processor capable of enabling/disabling memory access
AssigneeFujitsu Limited
InventorsMutsuhiro Naito, Kazuaki Mizoguchi
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Abstract
A low-end microprocessor 10 includes a stack pointer 18 storing a word SPV, a comparator 17 comparing the SPV with a given value ADR1, an inverter 19 inverting the compared result CP, and an AND gate 16 receiving a write request signal WR from a CPU 11 and the output of the inverter 19. The AND gate 16 provides its output to the write enable signal input WE of a memory 12 in order to determine enabling/disabling of writing according to the depth of stack.
Claims13
A processor, comprising:
- a first memory section having a stack area and receiving a first signal to enable access to said first memory section;
- a second memory section receiving a second signal to enable access to said second memory section;
- a processing section coupled to said first and second memory sections and having a register;
- a stack pointer specifying an address in said stack area where contents of said register are stored;
- and
- an access enable/disable determining circuit comparing contents of said stack pointer with a given value and outputting a comparison result indicative thereof, receiving said first signal, generating said second signal, and making said second signal active according to the comparison result when said first signal is active.
3 more elements
Dependencies are inferred from the claim text.