Fast suspend to disk

#Not applicable.

#1. Field of the Invention

#The present invention generally relates to data storage in computer systems. More particularly, the present invention relates to the manipulation of data that has been stored in random access memory during periods when the computer system is placed in a low power mode to minimize the latency that otherwise occurs when the system enters a low power mode and resumes operation from a low power mode.

#These and other aspects of the present invention will become apparent upon analyzing the drawings, detailed description and claims, which follow.

#For a detailed description of the preferred embodiments of the invention, reference will now be made to the accompanying drawings in which:

#FIG. 1 is a block diagram illustrating an exemplary computer system constructed according to the preferred embodiment;

#The present invention covers certain aspects of entering and exiting a low power state. There are three general aspects of a low power state described in the following detailed description: (a) performing a fast hibernation to minimize the amount of time it takes to hibernate data from the system memory to disk; (b) performing an instantaneous hibernation or hybrid suspend to disk operation; and (c) performing a fast resume from a suspend state. Each of these three aspects may be practiced independently of each other, or may be used in combination, as desired by the system designer or user.

#Referring initially to FIG. 1, a computer system 50 may comprise a personal computer, a web computer, a server, or a workstation, without limitation. Although not shown, the computer system 50 preferably couples via a suitable network connection to a local area network (LAN). As shown in FIG. 1, the computer system 50 preferably implements a standard computer architecture, including a CPU (or processor) 130, system memory 125, a memory controller 100, AGP video controller 140, and I/O controller 150. The processor 130 preferably couples to the memory controller 100 through host bus 135. It should be understood that other embodiments of the invention may include more than one processor or CPU coupled to the host bus. The processor may comprise any suitable microprocessor such as the Pentium II®, Pentium III®, or Celeron® processor by Intel®, the Athlon® processor by AMD, the Alpha processor by Compaq, or other microprocessors from these or other manufacturers that may be used or configured for use in a computer system.

#In accordance with normal convention, the CPU 130 executes programs and algorithms to control operation of the computer system. One such algorithm 132 is shown in FIG. 1. Although algorithm 132 is depicted separately from the CPU 130, it should be understood that the algorithm runs on the CPU 130, or some other device capable of executing algorithms. The algorithm 132 preferably controls the hibernation of data from the system memory 125 to non-volatile memory, as will be discussed in more detail below.