Memory device having posted write per command

A memory circuit comprising:

• a data buffer coupled to a storage array of said memory circuit;
• a logic circuit for receiving input data associated with a write command, said logic circuit being coupled to said data buffer and said storage array;
• a command decoder coupled to said logic circuit, said command decoder providing a first control signal to said logic circuit;
• and
• a controller coupled to said command decoder,
• wherein said controller determines if input data will be sent directly to said storage array or to said data buffer, said controller providing a second control signal to said command decoder, said command decoder in response to said second control signal providing said first control signal to said logic circuit, said first control signal being based on said second control signal, and said logic circuit in response to a first control signal sends said input data directly to said storage array or sends said input data to said data buffer.

A memory device comprising:

• an array of memory cells for storing data;
• a data buffer coupled to said array;
• a logic circuit coupled to said data buffer and said array,
• a latch coupled between said logic circuit and said array and coupled between said data buffer and said array;
• wherein when a write command to write input data to said array is received, said logic circuit, in response to a control signal, sends said input data associated with said write command directly to said array or sends said input data to said data buffer, said input data being latched by said latch before being sent to said array from said logic circuit or said data buffer.

A memory system comprising:

• a storage array for storing data, said data being input to said storage array in response to a write command and said data being extracted from said storage array in response to a read command;
• and
• a data buffer coupled to said storage array, said data buffer adapted to store input data associated with a write command;
• wherein
• said memory system includes circuitry for determining on a per command basis if input data associated with a write command is posted in said data buffer before being sent to said storage array,
• said input data associated with said write command is posted in said data buffer if a read command follows said write command, and
• wherein said input data posted in said buffer is sent to said storage array when output data associated with said read command is being output from said memory system.

A processing system comprising:

• a processing unit;
• and
• a memory device connected to said processing unit, said memory device comprising:
• an array of memory cells for storing data;
• a data buffer coupled to said array;
• a logic circuit coupled to said data buffer and said array;
• and
• a latch coupled between said logic circuit and said array and coupled between said data buffer and said array, said input data being latched by said latch before being sent to said array from said logic circuit or said data buffer
• wherein when a write command to write input data to said array is issued by said processing unit, said logic circuit, in response to a control signal, sends said input data associated with said write command directly to said array or sends said input data to said data buffer.

A processing system comprising:

• a processing unit;
• and
• a memory system connected to said processing unit, said memory system comprising:
• a storage array for storing data, said data being input to said storage array in response to a write command and said data being extracted from said storage array in response to a read command;
• and
• a data buffer coupled to said storage array, said data buffer adapted to store input data associated with a write command;
• wherein said memory system includes circuitry for determining on a per command basis if input data associated with a write command is posted in said data buffer before being sent to said storage array, and said input data associated with said write command is not posted in said data buffer if another write command follows said write command.

A method for writing input data associated with a write command into an array, said method comprising the steps of:

• receiving said input data associated with said write command;
• receiving a first control signal indicating said input data associated with said write command should be posted;
• posting said input data associated with said write command in response to said first control signal;
• receiving a second control signal indicating said input data associated with said write command should not be posted;
• sending said input data to said array without posting said input data in response to said second control signal;
• and
• latching said input data associated with said write command in a latch.

A method for posting input data associated with a write command, said method comprising the steps of:

• determining a next command following said write command;
• if said next command is a read command, posting said input data associated with said write command, otherwise not posting said input data associated with said write command;
• sending said input data associated with said write command to a data buffer;
• and
• storing said input data associated with said write command in said data buffer;
• determining a time period when input/output gates associated with a memory array are not being used;
• and
• sending said input data associated with said write command stored in said data buffer to said input data accociated with said write command stored in said data buffer to said memory array during said time period.