System and method utilizing speculative cache access for improved performance

A method of accessing a cache, said method comprising the steps of:

• inputting a memory access request into a cache structure;
• first receiving a virtual address for said memory access request in a TLB, wherein said TLB begins translation of said received virtual address to a physical address and wherein at least one bit of said virtual address is the same for said physical address;
• then in parallel with said TLB translating said received virtual address to a physical address, beginning an access of said cache structure's tags using at least one of said at least one bit of said virtual address that is the same for said physical address;
• once a physical address is output by said TLB, beginning a decode of at least part of said physical address to access said cache structure's data array(s);
• and
• in parallel with said decode, using MESI protocol to verify that a true tag hit is achieved for said cache structure.

A computer system comprising:

• at least one processor that executes instructions;
• multi-level cache structure accessible by said at least one processor to satisfy memory access requests, wherein each level of said multi-level cache structure comprises a data array and corresponding decode circuitry for said data array and wherein said multi-level cache structure is configured to receive into decode circuitry of a level of said multi-level cache structure at least a portion of a memory address for a received memory access request without first determining whether a memory address required to satisfy said received memory access request is truly present in said data array of said level of said multi-level cache structure;
• and
• wherein said level of said multi-level cache structure comprises tag match circuitry operable to determine whether a tag hit is achieved for said memory address in said level, and wherein said tag match circuitry is configured to receive at least part of said memory address before said decode circuitry of said level decodes said memory address.

A multi-level cache structure that is accessible to at least one computer processor to satisfy memory access requests for instructions being executed by said at least one computer processor, said multi-level cache structure comprising:

• a data array for each level of said multi-level cache structure;
• means for receiving a memory access request from at least one processor;
• means for beginning decode of a memory address for a received memory access request for multiple levels of said multi-level cache structure's data arrays in parallel without having first determined whether a memory address required to satisfy said received memory access request is truly present in said multi-level cache structure;
• and
• means for determining whether said memory address required to satisfy said received memory access request is truly present in a level of said multi-level cache, wherein said means for beginning decode begins said decode for said level in parallel with execution of the determining means.

A computer system comprising:

• at least one processor that executes instructions synchronous with a clock;
• multi-level cache structure accessible by said at least one processor to satisfy memory access requests;
• said multi-level cache structure comprising a TLB that receives a virtual address for a memory access request and outputs a corresponding physical address, a data array structure that is capable of being accessed to satisfy said memory access request, decode circuitry that decodes at least a portion of a physical address output by said TLB to determine a physical address to access in said data array structure, tag match circuitry that determines whether a tag hit is achieved for said multi-level cache structure for said memory access request, and MESI circuitry that determines whether said tag hit is a true tag hit;
• and
• wherein said multi-level cache is implemented such that said decode circuitry begins executing in a same cycle of said clock that said MESI circuitry is executing for determining whether said tag hit is a true tag hit.