High bandwidth-low latency memory controller

A computer program product for controlling at least three parallel-coupled memory controller subsystems, comprising:

• computer code for queuing read commands and write commands to be sent to the memory in at least one read/write queue with an input coupled to a computer component and an output coupled to memory;
• computer code for queuing precharge commands to be sent to the memory in a precharge queue with an input coupled to the computer component and an output coupled to the memory;
• and
• computer code for queuing activate commands to be sent to the memory in an activate queue with an input coupled to the computer component and an output coupled to the memory;
• wherein the precharge commands and the activate commands are queued in parallel for reducing the latency and increasing bandwidth associated with accessing the memory;
• wherein a first one of the memory controller subsystems is coupled to a graphics unit computer component, a second one of the memory controller subsystems is coupled to a central processing computer component, and a third one of the memory controller subsystems is coupled to a display refresh module computer component.

A memory controller system, comprising:

• a plurality of memory controller subsystems coupled to a plurality of computer components, each memory controller subsystem including:
• at least one read/write queue with an input coupled to one of the computer components and an output coupled to memory for queuing read commands and write commands to be sent to the memory, and
• at least one precharge/activate queue with an input coupled to one of the computer components and an output coupled to the memory for queuing precharge and activate commands to be sent to the memory;
• wherein the precharge commands and the activate commands are capable of being restored to a row and a bank associated with the read commands and write commands at a head of the read/write queue.

A memory controller system, comprising:

• a plurality of memory controller subsystems coupled to a plurality of computer components, each memory controller subsystem including:
• (a) at least one read/write queue with an input coupled to one of the computer components and an output coupled to memory for queuing read commands and write commands to be sent to the memory, and
• (b) at least one precharge/activate queue with an input coupled to one of the computer components and an output coupled to the memory for queuing precharge and activate commands to be sent to the memory;
• wherein the at least one precharge/activate queue includes a precharge queue with an input coupled to one of the computer components and an output coupled to the memory for queuing precharge commands to be sent to the memory, and an activate queue with an input coupled to one of the computer components and an output coupled to the memory for queuing activate commands to be sent to the memory;
• wherein the precharge commands in the precharge queue and the activate commands in the activate queue are capable of being restored to a row and a bank associated with the read commands and write commands at a head of the read/write queue.

A method for controlling memory utilizing a memory controller, comprising:

• receiving a plurality of read commands, write commands, precharge commands and activate commands from a plurality of queues capable of being loaded from a plurality of computer components independent of the state of the memory;
• arbitrating the delivery of the read commands, write commands, precharge commands and activate commands from the queues to the memory;
• and
• delivering the arbitrated read commands, write commands, precharge commands and activate commands to the memory;
• wherein the memory controller is capable of restoring the precharge commands and the activate commands to a row and a bank associated with the read commands and write commands at a head of a read/write queue.

A method for controlling memory, comprising:

• (a) receiving a plurality of read commands, write commands, precharge commands and activate commands from a plurality of queues capable of being loaded from a plurality of computer components independent of the state of the memory;
• (b) arbitrating the delivery of the read commands, write commands, precharge commands and activate commands from the queues to the memory;
• and
• (c) delivering the arbitrated read commands, write commands, precharge commands and activate commands to the memory;
• wherein the method is carried utilizing a memory controller coupled to the queues, the queues including:
• (i) at least one read/write queue with an input coupled to one of the computer components and an output coupled to the memory for queuing read commands and write commands to be sent to the memory,
• (ii) a precharge queue with an input coupled to one of the computer components and an output coupled to the memory for queuing precharge commands to be sent to the memory, and
• (iii) an activate queue with an input coupled to one of the computer components and an output coupled to the memory for queuing activate commands to be sent to the memory;
• wherein the memory controller is capable of restoring the precharge commands in the precharge queue and the activate commands in the activate queue to a row and a bank associated with the read commands and write commands at a head of the read/write queue.

A computer program product for controlling memory utilizing a memory controller, comprising:

• computer code for receiving a plurality of read commands, write commands, precharge commands and activate commands from a plurality of queues capable of being loaded from a plurality of computer components independent of the state of the memory;
• computer code for arbitrating the delivery of the read commands, write commands, precharge commands and activate commands from the queues to the memory;
• and
• computer code for delivering the arbitrated read commands, write commands, precharge commands and activate commands from the queues to the memory;
• wherein the memory controller is capable of restoring the precharge commands in a precharge queue and the activate commands in an activate queue to a row and a bank associated with the read commands and write commands at a head of a read/write queue.

A memory controller for controlling memory utilizing a memory controller, comprising:

• logic for receiving a plurality of read commands, write commands, precharge commands and activate commands from a plurality of queues capable of being loaded from a plurality of computer components independent of the state of the memory;
• logic for arbitrating the delivery of the read commands, write commands, precharge commands and activate commands from the queues to the memory;
• and
• logic for delivering the arbitrated read commands, write commands, precharge commands and activate commands from the queues to the memory;
• wherein the memory controller is capable of restoring the precharge commands in a precharge queue and the activate commands in an activate queue to a row and a bank associated with the read commands and write commands at a head of a read/write queue.