Multiprocessor computer systems with command FIFO buffer at each target device
AssigneeCradle Technologies, Inc.
InventorCecil H. Kaplinsky
Life of this patent
Estimating the term…
Abstract
A multiprocessor computer system in which each processor being used as a target device has a FIFO (first in first out) buffer for receiving and storing transfer commands from a split transactional global bus for later execution. The transfer commands are put in the FIFO of the target device in the order of their arrival and are taken out of the FIFO and executed by the target device in the same order. This eliminates the wasting of bus time that occurs when busy signals are sent from target devices to master devices and when transfer commands are resent from master devices to target devices. Therefore, the present invention eliminates the wasting of bus time related to transfer commands being rejected.
Claims30
A multiprocessor computer system comprising:
- a) a split transaction global bus;
- b) at least one target device connected to the split transaction global bus, the at least one target device having a command FIFO buffer for storing a command issued by the split transaction global bus to the target device such that the at least one target device may accept the issued command both while it is executing a previously-issued command and while it is not executing any command;
- and
- c) a plurality of master devices connected to the split transaction global bus and having means for releasing the split transaction global bus for use by another device connected to the split transaction global bus after receiving an acknowledgment of command receipt from the at least one target device.
A method of preventing a bus in a multiprocessor computer system from being blocked comprising:
- a) sending a command from a master device to a split transaction global bus;
- b) placing the command in a command FIFO of a target device;
- c) sending the master device an acknowledgement of command receipt;
- d) releasing the split transaction global bus for use by other bus devices, where such use includes another master device issuing a command accepted by the target device while the target device is executing a previously-issued transaction;
- and
- e) repeating steps a)-d) as necessary.
Dependencies are inferred from the claim text.