Data synchronization interface
AssigneeIntel Corporation
InventorsJonathan C. Lueker, Dean Warren
Life of this patent
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Abstract
Incoming serial data which is received M bits at a time where M=N, N+1 or N−1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.
Claims23
A method for synchronizing data comprising:
- a. receiving data M bits at a time, where M varies between N, N+1 and N−1 and N is greater than 1;
- and
- b. outputting data R bits at a time where R=(M*X)+1 where X is an integer greater than one.
Apparatus for synchronizing data comprising:
- a. a data rotator having N+1 data inputs coupled to receive M bits of said data where M varies between N, N+1 and N−1 and N is greater than 1 and having 3*(N+1) outputs;
- b. a register having 3*(N+1) bit locations, 3*(N+1) inputs and 3*(N+1) outputs;
- c. a plurality of 3*(N+1) multiplexers each having 3 inputs and an output, the respective 3*(N+1) outputs of said multiplexers coupled to the respective 3*(N+1) inputs of said register, the respective the first (N+1) outputs of said register coupled to respective second inputs of the first (N+1) of said multiplexers, the second (N+1) outputs of said register coupled to respective third inputs of said first (N+1) of said multiplexers;
- d. R output lines, from the first R of said 3*(N+1) outputs of said register providing a final output of said apparatus where R=(M*X)+1 where X is an integer greater than one;
- and
- e. a control unit providing control inputs to said rotator, said register and said multiplexers.
Apparatus according to claim ii wherein said rotator is a barrel shifter.
A computer readable memory containing program instructions that, when executed by a processor, cause the processor to:
- a. receive a first M bits of said data where M varies between N, N+1 and N−1 and N is greater than 1;
- b. store said first M bits;
- c. receive M additional bits;
- d. store said M additional bits;
- e. repeat c. and d. until at least a predetermined number R of bits have been stored, where R=(M*X)+1 where X is an integer greater than one;
- f. output the first R bits;
- g. continue to store any remaining S bits in excess of R;
- and
- h. continually repeat c.-g.
Dependencies are inferred from the claim text.