US 6,647,405 B1 · Adder circuit, integrating circuit which uses the adder circuit, and synchronism detection circuit which uses the integrating circuit

Abstract

An adding circuit which receives addend data and augend data, each of which consists of a plurality of bits, and sums the addend and augend data, comprises: a plurality of addition blocks, each of which is used to add a predetermined number of bits of the addend data to a like number of bits of the augend data, and for outputting both the result obtained by adding the predetermined number of bits and a carry-out signal, wherein, when a carry-out occurs for one of the addition blocks, in accordance with a carry-out signal from a lower rank and a set comprising the addend data and the augend data, the pertinent addition block responds to the pertinent carry-out, and wherein, when a carry-out does not occur for the addition block in accordance with the set comprising the addend data and the augend data, the pertinent addition block responds to the carry-out and generates a block addition end signal which indicates that the addition performed by the addition block has been completed.

Claims15

Dependent claims

An adder circuit, which receives addend data and augend data, each of which consists of a plurality of bits, and sums said addend and augend data, comprising:

a plurality of adder blocks, each of which has an adder for adding a predetermined number of bits of said addend data to the predetermined number of bits of said augend data, and for outputting both the addition result having said predetermined number of bits and a carry-out signal,
wherein, each adder block further has a block addition end signal generator for generating a block addition end signal which indicates that the addition performed by said adder block has been completed, said block addition end signal generator including a carry detection decoder for detecting a carry-out of said adder block by decoding a carry-out signal from a lower adder block, said addend data, and said augend data,
said block addition end signal generator;
generating said block addition end signal in response to the carry-out of the adder block, when the carry-out is detected by the carry detection decoder, and not in response to the carry-out of the adder block, when the carry-out is not detected by the carry detection decoder.

1 more element

An integrating circuit comprising:

an adder circuit, which receives addend data and augend data, each of which consists of a plurality of bits, and sums said addend and augend data, having
a plurality of adder blocks, each of which has an adder for adding a predetermined number of bits of said addend data to the predetermined number of bits of said augend data, and for outputting both the addition result having said predetermined number of bits and a carry-out signal,
wherein, each adder block further has a block addition end signal generator for generating a block addition end signal which indicates that the addition performed by said adder block has been completed, said block addition end signal generator including a carry detection decoder for detecting a carry-out of said adder block by decoding a carry-out signal from a lower adder block, said addend data, and said augend data,
said block addition end signal generator generating said block addition end signal in response to the carry-out of the adder block, when the carry-out is detected by the carry detection decoder, and not in response to the carry-out of the adder block, when the carry-out is not detected by the carry detection decoder, and
block addition end signals are received from said plurality of adder blocks, and in response to the timing at which all the block addition end signals indicate addition has been completed, an addition end signal for said adder circuit is generated;
an addend data input buffer for recording the addend data;
and
an addition result buffer for recording the results of the addition and for outputting the augend data,
wherein, in response to the addition end signal, said addend data and said augend data are supplied from said addition data input buffer and said addition result buffer to the plurality of adder blocks.

6 more elements

A synchronism detection circuit, which detects the synchronism of diffusion code for a received signal subject to a code diffusion, comprising:

an integrating circuit including,
an adder circuit, which receives addend data and augend data, each of which consists of a plurality of bits, and sums said addend and augend data, having
a plurality of adder blocks, each of which has an adder for adding a predetermined number of bits of said addend data to the predetermined number of bits of said augend data, and for outputting both the addition result having said predetermined number of bits and a carry-out signal,
wherein, each adder block further has a block addition end signal generator for generating a block addition end signal which indicates that the addition performed by said adder block has been completed, said block addition end signal generator including a carry detection decoder for detecting a carry-out of said adder block by decoding a carry-out signal from a lower adder block, said addend data, and said augend data,
said block addition end signal generator generating said block addition end signal in response to the carry-out of the adder block, when the carry-out is detected by the carry detection decoder, and not in response to the carry-out of the adder block, when the carry-out is not detected by the carry detection decoder, and
block addition end signals are received from said plurality of adder blocks, and in response to the timing at which all the block addition end signals indicate addition has been completed, an addition end signal for said adder circuit is generated;
an addend data input buffer for recording the addend data;
and
an addition result buffer for recording the results of the addition and for outputting the augend data,
wherein, in response to the addition end signal, said addend data and said augend data are supplied from said addition data input buffer and said addition result buffer to the plurality of adder blocks;
a plurality of delay circuits, each of which delays said received signal having a plurality of bits;
and
a plurality of multiplication circuits for multiplying by the outputs of said plurality of delay circuits and the diffusion code having a plurality of bits respectively,
wherein the outputs of said multiplication circuits are accumulated by said integrating circuit, and said synchronism is detected according to the accumulation result.

11 more elements