Arithmetic and control unit

An arithmetic and control unit comprising,

• a monitor unit provided with a clock/transfer means which counts a cycle time by receiving diagnostic pulses and when the cycle time is decided to be larger than a prescribed overflow decision time, stores temporarily an overflow bit by giving a prescribed state value to it and after a lapse of a prescribed time outputs an overflow bit signal having a signal level corresponding to the state value of the temporarily stored overflow bit, and outputs a reset instruction signal at an active level during said prescribed time when said temporarily stored overflow bit is said prescribed state value, and clears said temporarily stored overflow bit when it receives an active level of an overflow bit clear signal, and a reset signal output means which outputs a pulse-form reset signal based on said reset instruction signal, and
• a control unit provided with a diagnostic pulse generation/failure decision means which outputs said diagnostic pulse to said monitor unit at every completion of normal execution of a unit control operation, receives said overflow bit signal and stores the state value of the overflow bit and outputs said overflow bit clear signal to said monitor unit, then if the stored overflow bit is not said prescribed state value, stops the output of said diagnostic pulse during a monitor unit inspection time which is larger than said overflow decision time by deciding the state to be an initial activation, and when an active level of an internal reset signal is not received within said monitor unit inspection time, outputs a failure warning instruction signal, and if the overflow bit is said prescribed state value, outputs said failure warning instruction signal when the number of times of overflow occurrence updated by increasing the number of times of overflow occurrence stored in a nonvolatile memory by 1 (one) exceeds a prescribed allowable number of times, a failure warning means which outputs a failure warning signal to the outside when said failure warning instruction signal goes to active level, and a reset signal input means which outputs said internal reset signal upon receipt of said reset signal from said monitor unit.

An arithmetic and control unit comprising,

• a monitor unit provided with a clock means which counts a cycle time by receiving diagnostic pulses and regards it as an overflow and imparts a prescribed state value to an overflow bit when it decides that the cycle time is larger than a prescribed overflow decision time, an overflow bit transfer means which stores temporarily the overflow bit received from said clock means and after a lapse of a prescribed time outputs the overflow bit as a signal level corresponding to the state value of the temporarily stored overflow bit and if said temporarily stored overflow bit is said prescribed state value, outputs a failure warning instruction signal and outputs a reset instruction signal as an active level, and clears said temporarily stored overflow bit when it receives active level of an overflow bit clear signal, an abnormality warning means which outputs an abnormality warning signal upon receipt of active level of said abnormality warning instruction signal, and a reset signal output means which outputs a pulse-form reset signal based on said reset instruction signal, and
• a control unit provided with a main control means which calculates a controlled value of a wheel based on signals from a wheel speed sensor of an antilock brake control device and outputs a control signal to the outside and instructs the output of a diagnostic pulse at every normal execution of a unit control operation, a failure decision means which receives the overflow bit signal from said monitor unit and stores the state value of the overflow bit and outputs said overflow bit clear signal to said monitor unit, then if the stored overflow bit is not the prescribed state value corresponding to the overflow, outputs a monitor unit inspection instruction signal by deciding that it is an initial activation, and if said stored overflow bit is said prescribed state value, decides that it is a reactivation and outputs a first failure warning instruction signal when the updated number of times of overflow occurrence obtained by increasing the number of times of overflow occurrence by 1 (one) exceeds a prescribed allowable number of times, a diagnostic pulse generating means which outputs a diagnostic pulse to said monitor unit upon receipt of a diagnostic pulse output instruction, and when receives active level of said monitor unit inspection instruction signal, stops the generation of the diagnostic pulse during a monitor unit inspection time which is larger than said overflow decision time and generates a second failure warning instruction signal if the internal reset signal is not received within said monitor unit inspection time, a failure warning means which outputs a failure warning signal continuously to the outside when either one of said first failure warning signal or said second failure warning signal went to active level, and a reset signal input means which receives said reset signal and supplies said reset signal to at least said main control means, said diagnostic pulse generating means, and said failure decision means.