Parallel pipeline processing system

Abstract

A pipelined parallel processor (PPP) integrated circuit includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits include, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch that routes data among the frame store controller, filtering unit, function circuits, external input channels, and external output channels. The internal frame store controller includes a plurality of programmable video line store memories that are coupled to an external field or frame store memory. Each line store memory may be programmed to provide data to, or receive data from one of the PPP components by a controller and to transfer the data from or to the memory, respectively. Access to the external memory by the line store memories is controlled by an arbitration processor which implements a priority scheme.

Dependencies are inferred from the claim text.