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US 6,647,081 B2Granted
Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
AssigneeEmulex Corporation
InventorsJim Butler, Raul Oteyza
Life of this patent
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Abstract
A phase-locked loop (PLL) circuit includes multiple selectable feedback paths and a mode selector for selecting different feedback paths in different operating modes. The PLL circuit may correct for clock skew or produce a desired degree of clock skew between input and output clock signals in different operating modes.
Claims10
Apparatus comprising:
- an input node operative to receive a first clock signal;
- an output node operative to receive a second clock signal;
- a phase-locked loop circuit including a first feedback path and a second feedback path, each of said feedback paths operative to introduce a different degree of skew between the first clock signal and the second clock signal;
- a feedback path selector operative to select one of said feedback paths;
- and
- a clock signal path between the input node and the output node, the clock signal path comprising a first delay-inducing element,
- wherein the second feedback path comprises said first delay-inducing element and one or more additional delay-inducing elements operative to overcorrect for a skew between said input signal and said output signal caused by the first delay-inducing element.
4 more elements
Apparatus comprising:
- an input node operative to receive an input signal;
- an output node operative to receive an output signal;
- a clock signal path between the input node and the output node, said clock signal path including a clock tree;
- a phase-locked loop circuit including
- a first feedback path including the clock tree, and
- a second feedback path including a string of buffers;
- and
- a mode selector operative to select the first feedback path in a first operating mode and to select the second feedback path in a second operating mode,
- wherein the first operating mode has a clocking scheme requiring substantially no skew between said input and output signals, and
- wherein the second operating mode has a clocking scheme requiring a degree of skew between said input and output signals.
7 more elements
Apparatus comprising:
- an input node operative to receive an input signal;
- an output node operative to receive an output signal;
- a clock signal path between the input node and the output node, said clock signal path including a clock tree;
- a phase-locked loop circuit including
- a first feedback path including the clock tree, and
- a second feedback path including a string of buffers;
- and
- a mode selector operative to select the first feedback path in a first operating mode and to select the second feedback path in a second operating mode,
- wherein the second feedback path includes the clock tree.
6 more elements
Apparatus comprising:
- an input node operative to receive an input signal;
- an output node operative to receive an output signal;
- a clock signal path between the input node and the output node, said clock signal path including a clock tree;
- a phase-locked loop circuit including
- a first feedback path including the clock tree, and
- a second feedback path including a string of buffers;
- and
- a mode selector operative to select the first feedback path in a first operating mode and to select the second feedback path in a second operating mode,
- wherein the phase-locked loop (PLL) circuit includes a PLL input node, and further comprising a delay-inducing element between the input node and the PLL input node.
6 more elements
Dependencies are inferred from the claim text.