A circuit configuration for compensating for interference in a signal generated by discrete multitone modulation, the signal generated by discrete multitone modulation having a multiplicity of carrier frequencies in the frequency domain, and each carrier frequency having a signal vector, comprising:
- a first decision circuit receiving a reference signal vector, said first decision circuit mapping the reference signal vector into a value-discrete reference signal vector;
- a subtractor circuit connected to said first decision circuit for forming an error signal vector by subtracting the reference signal vector and the value-discrete reference signal vector from one another;
- a multiplicity of adders receiving the error signal vector and adding the error signal vector to each of the remaining signal vectors, except for the reference signal vector;
- and
- multiplier circuits connected upstream of each of said adders in a signal flow direction, said multiplier circuits multiplying the error signal vector by adjustable coefficients.