Digital tuner with optimized clock frequency and integrated parallel CIC filter and local oscillator

Abstract

A digital tuner 70 for maximizing tuning range for a particular intermediate frequency includes an analog to digital converter (78) operating at an input clock frequency to sample an analog input signal (76) and output a multi-bit digital word for each sample, a demultiplexer (82) in communication with the analog to digital converter (78) and a plurality of mixers (84) to convert serial samples from the analog to digital converter (78) to parallel samples for input to the mixers (84) functioning as quadrature multipliers, local oscillators (86) in communication with corresponding ones of the mixers (84), and a parallel cascaded integrator comb filter (72, 74) in communication with the mixers (84) for filtering and decimating the parallel samples, where the mixers (84), the local oscillators (86), and the filter (72, 74) operate at a frequency having adjacent harmonics substantially centered about the intermediate frequency. A method for determining an operating frequency for a digital tuner having an associated intermediate frequency to reduce clock harmonic interference includes determining a maximum frequency based on operating parameters of tuner elements, selecting a harmonic of the operating frequency based on the intermediate frequency and the maximum frequency, and selecting the operating frequency based on the intermediate frequency.

Dependencies are inferred from the claim text.