Network switch using network processor and methods

A scalable Network Processor comprising:

• a processing complex including N processors, N>1;
• a plurality of input/output ports;
• at least one UP Side Media Access Control (MAC) module that processes ingress data received from input ports;
• an UP Side EnQue/DeQue Scheduler positioned in an up path and operatively coupled to the processing complex and the UP Side MAC;
• at least one DOWN Side MAC positioned in a down path and coupled to the output ports, said at least one DOWN Side MAC processing egress data and forwarding the processed data to output ports;
• a DOWN Side EnQue/DeQue Scheduler positioned in said down path and operatively coupled to the processing complex and the at least one DOWN Side MAC;
• and
• a connector system operatively coupling the UP Side EnQue/DeQue Scheduler and the DOWN Side EnQue/DeQue Scheduler so that the input/output ports in a single Network Processor or M Network Processors, M≧2, are operatively interconnected wherein data is exchanged between input/output ports in the single Network Processor or the M Network Processors.