Synchronous controlled, self-timed local SRAM block
AssigneeBroadcom Corporation
InventorsGil I. Winograd, Esin Terzioglu, Ali Anvar, Sami Issa
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Abstract
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.
Claims20
A memory device comprising:
- a synchronous controlled global element;
- and
- a self-timed local element interfacing with said synchronous controlled global element.
A memory device comprising:
- a synchronous controlled global element;
- a self-timed local element interfacing with said synchronous controlled global element, wherein said local elements comprises:
- a plurality of memory cells forming at least one cell array;
- at least one local decoder interfacing with said at least one cell array;
- at least one local sense amplifier interfacing with said local decoder and said cell array and adapted to precharge and equalize at least one line coupled thereto;
- and
- at least one local controller interfacing with and coordinating at least said local decoder and sense amplifier.
A synchronous self-timed memory structure comprising:
- a plurality of memory cells forming at least one cell array;
- at least one local decoder interfacing with said at least one cell array;
- at least one local sense amplifier interfacing with at least said one decoder and said cell array and adapted to precharge and equalize at least one line coupled thereto;
- at least one local controller interfacing with and coordinating said local decoder and sense amplifier.
A hierarchical memory structure that comprises a logical portion of a larger memory device, the hierarchical memory structure comprising:
- a plurality of memory cells forming at least one cell array;
- at least one local decoder interfacing with said at least one cell array;
- at least one local sense amplifier interfacing with said at least one decoder and said at least one cell array and adapted to precharge and equalize at least one line coupled thereto;
- and
- at least one local controller interfacing with and coordinating said at least one local decoder and said at least one sense amplifier.
A method of performing a read operation using a memory device containing at least one logical memory subsystem, the method comprising:
- selecting at least one cell array;
- selecting at least one sub-block in the logical memory subsystem;
- isolating at least one local sense amplifier;
- activating a local wordline;
- discharging at least one bitline in at least one bitline pair;
- developing a differential voltage across said bitline pair;
- stopping said discharge;
- and
- equalizing and precharging said bitline pair.
Dependencies are inferred from the claim text.