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US 6,646,953 B1Granted
Single-clock, strobeless signaling system
AssigneeRambus Inc.
InventorDonald C. Stark
Life of this patent
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Abstract
A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
Claims51
A memory system comprising:
- a signaling path;
- a memory controller coupled to the signaling path;
- a clock generator to generate a first clock signal;
- and
- a memory device coupled to the signaling path and to the clock generator, the memory device including timing circuitry to generate a second clock signal having a first phase offset, relative to the first clock signal, that is determined at least in part by a signal propagation time on the signaling path, wherein the memory device further includes receive circuitry to receive information from the memory controller via the signaling path under timing control of the second clock signal.
2 more elements
A memory system comprising:
- a signaling path;
- a memory controller coupled to the signaling path;
- a clock generator to generate a first clock signal;
- and
- a memory device coupled to the signaling path and to the clock generator, the memory device including timing circuitry to generate a second clock signal having a first phase offset, relative to the first clock signal, that is determined at least in part by a signal propagations time on the signaling path, wherein the first phase offset represents a combination of phase offset components including a first component to advance the phase of the second clock signal relative to the first clock signal according to the signal propagation time, wherein the memory device further includes transmit circuitry to transmit information to the memory controller via the signaling path under timing control of the second clock signal.
2 more elements
A memory system comprising:
- a signaling path;
- a memory controller coupled to the signaling path;
- a clock generator to generate a first clock signal;
- and
- a memory device coupled to the signal path and to the clock generator, the memory device including timing circuitry to generate transmit and receive clock signals having respective phase offsets from the first clock signal according to respective transmit and receive phase offset values within the memory device.
2 more elements
A semiconductor memory device comprising:
- a clock input to receive a first external clock signal;
- and
- timing circuitry including a receive phase offset register and a transmit phase offset register, the timing circuitry being coupled to the clock input to generate receive and transmit clock signals having respective phase offsets from the first external clock signal according to respective phase offset values within the receive and transmit phase offset registers.
A memory controller comprising:
- a signaling interface to communicate with a memory device;
- and
- calibration control circuitry to communicate with the memory device via the signaling interface in a calibration operation to determine transmit and receive phase offset values that are applied to timing circuitry within the memory device to generate respective transmit and receive clock signals, the transmit phase offset value representing a phase offset between the transmit clock signal and a second clock signal supplied to a clock input of the memory device, and the receive phase offset value representing a phase offset between the receive clock signal and the second clock signal.
A method of communicating information between a memory controller and a memory device, the method comprising:
- generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller;
- timing communication of information between the memory device and the memory controller on the signaling path using the first clock signal, wherein timing communication of information between the memory device and the memory controller comprises transmitting information from the memory device to the memory controller under timing control of the first clock signal;
- generating a third clock signal within the memory device, the third clock signal having a phase offset relative to the second clock signal that is determined at least in part by the signal propagation time;
- and
- receiving information from the memory controller within the memory device under timing control of the third clock signal.
2 more elements
A method of communicating information between a memory controller and a memory device, the method comprising:
- generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller;
- and
- timing communication of information between the memory device and the memory controller on the signaling path using the first clock signal, wherein generating a first clock signal having a phase offset relative to a second clock signal comprises offsetting the phase of the first clock signal relative to the second clock signal according to value stored in a phase offset register within the memory device.
A method of communicating information between a memory controller and a memory device, the method comprising:
- generating a first clock signal within the memory device, the first clock signal having a phase offset relative to a second clock signal that is determined at least in part by a signal propagation time on a signaling path between the memory device and the memory controller;
- and
- timing communication of information between the memory device and the memory controller on the signaling path using the first clock signal, wherein timing communication of information between the memory device and the memory controller comprises receiving information from the memory controller within the memory device under timing control of the first clock signal.
A method of communicating information between a memory controller and a memory device, the method comprising:
- generating, within the memory device, transmit and receive clock signals that have respective phase offsets from a reference clock signal according to values stored in respective transmit and receive phase offset registers within the memory device;
- transmitting information from the memory device to the memory controller in response to transitions of the transmit clock signal;
- and
- receiving information from the memory controller in the memory device in response to transitions of the receive clock signal.
1 more element
A method of operation within a semiconductor memory device, the method comprising:
- generating transmit and receive clock signals that have respective phase offsets from a reference clock signal according to values stored in respective transmit and receive phase offset registers within the memory device;
- transmitting information via an external signal path in response to transitions of the transmit clock signal;
- and
- receiving information via the external signal path in response to transitions of the receive clock signal.
1 more element
A method of controlling a semiconductor memory device within a memory system, the method comprising:
- communicating with the memory device in a calibration operation to determine a transmit phase offset value that is applied to timing circuitry within the memory device to generate a transmit clock signal, the transmit phase offset value representing a phase offset between the transmit clock signal and a second clock signal supplied to a clock input of the memory device;
- and
- communicating with the memory device in a calibration operation to determine a receive phase offset value that is applied to timing circuitry within the memory device to generate a receive clock signal, the receive phase offset value representing a phase offset between the receive clock signal and the second clock signal.
Dependencies are inferred from the claim text.