High performance address decode technique for arrays
AssigneeSun Microsystems, Inc.
InventorsShree Kant, Aparna Ramachandran
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Abstract
An address decoder having pre-decode logic circuitry positioned in between ends of final decode logic circuitry is provided. Such an address decoder yields less wire load, less gate load, less power consumption, and increased speed due to the pre-decode logic circuitry having to be capable of only driving a signal over half the length of a final decoder. Further, a method to select memory elements from a memory array using centrally positioned pre-decode logic circuitry is provided.
Claims18
An address decoder for a memory array, comprising:
- a pre-decode stage comprising logic circuitry adapted to partially decoding an address input;
- and
- a final decode stage comprising additional logic circuitry adapted to further decoding the partially decoded address input and selecting an address line within the memory array,
- wherein the logic circuitry of the pre-decode stage comprises:
- a first set of logic gates, and
- a second set of logic gates,
- wherein the logic gates of the first set input a first combination of one or more bits of the address input,
- wherein the logic gates of the second set input a second combination of one or more bits of the address input, and
- wherein the first combination and the second combination are chosen such that lengths of wires from the first set of logic gates to the final decode stage are substantially the same and lengths of wires from the second set of logic gates to the final decode stage are substantially the same.
A method for decoding an address in order to select a memory element of a memory array, comprising:
- inputting a first combination of one or more address bits to a first set of logic gates;
- inputting a second combination of one or more address bits to a second set of logic gates;
- and
- outputting signals from the first set of logic gates and the second set of logic gates to logic gates in a final decode stage,
- wherein the first combination and the second combination are chosen such that lengths of wires from the first set of logic gates to the final decode stage are substantially the same and lengths of wires from the second set of logic gates to the final decode stage are substantially the same.
A method for connecting circuitry of a decoder, comprising:
- determining a first combination of bits and a second combination of bits of an address input to an address decoder of a memory array;
- configuring pre-decode logic circuitry of the address decoder such that the first combination of bits corresponds to a first set of logic gates;
- and
- configuring the pre-decode logic circuitry such that the second combination of bits corresponds to a second set of logic gates,
- wherein the determining is performed such that lengths of wires from the first set of logic gates to the decoder are substantially the same and lengths of wires from the second set of logic gates to the decoder are substantially the same.
Dependencies are inferred from the claim text.