Word line driver for dynamic random access memories

A word line driver for a memory element of a dynamic random access memory comprising:

• a word line connected to a plurality of memory elements;
• a first transistor connected to a source of negative potential and to said word line for switching said word line to said source of negative potential in response to a first decoder signal RDOUT;
• diode connected to said word line and to receive a selector signal WLRST;
• and
• a second transistor connected to a selector signal WDRV which switches between a positive potential and zero volts, and to said word line, said second transistor having a gate connected to receive a signal bRDOUT which is a delayed complement to said decoder signal RDOUT, said second transistor driving said word line to a positive potential in response to said selector signal WLRST being at said substantially positive potential, and in response to said decoder complement signal bRDOUT being, and said word line being driven first to substantially zero volts through said diode when said selector signal WLRST is at zero volts and said RDOUT signal enables said first transistor, and then to substantially said negative potential through said first transistor.