Data transfer control device, semiconductor memory device and electronic information apparatus

A data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command and each of data transfer start addresses and data transfer completion addresses of the first and second memory arrays, the device comprising:

• a command recognition section for recognizing the input control command;
• a first address output section for outputting a data transfer start address of the first memory array, a data transfer completion address of the first memory array, and a data transfer start address of the second memory array based on the input control command in this storage order or outputting the data transfer start address of the second memory array, data transfer completion address of the second memory array and data transfer start address of the first memory array based on the input control command in this storage order;
• a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section;
• a first memory address counter section for incrementing a memory address for each unit of data transfer;
• a first memory address transfer section for transferring the data transfer start address from the first memory address storage section to the first memory address counter section;
• a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section;
• a second memory address counter section for incrementing a memory address for each unit of data transfer;
• a second memory address transfer section for transferring the data transfer start address from the second memory address storage section to the second memory address counter section;
• a third memory address storage section for storing the data transfer completion address output from the first address output section;
• a first comparison section for comparing a value of the data transfer completion address and a value of the first or second memory address counter section;
• a first comparison target address switch section for controlling a switch between values of the first and second memory address counter sections targeted for comparison to the data transfer completion address based on the input control command so as to compare the value of the data transfer completion address to any one of the values of the first and second memory address counter sections;
• and
• a first data transfer control section for performing the mutual data transfer between the first and second memory arrays based on address values set in the first and second memory address counter sections and completing the mutual data transfer based on a comparison result obtained by the first comparison section.

A data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command, data transfer start addresses and a data transfer completion address of the first and second memory arrays, and the number of batches of data to be transferred, the device comprising:

• a command recognition section for recognizing the input control command;
• a second address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command;
• a first memory address storage section for storing the data transfer start address of the first memory array output from the second address output section;
• a second memory address storage section for storing the data transfer start address of the second memory array output from the second address output section;
• a transfer data number storage section for storing the number of batches of data to be transferred output from the second address output section;
• a data counter section for incrementing the number of batches of data for each data transfer unit;
• a second comparison section for comparing the number of batches of data to a value of the data counter section;
• and
• a second data transfer control section performing the mutual data transfer between the first and second memory arrays based on values obtained by sequentially incrementing address values of the first and second memory address storage sections and completing the mutual data transfer based on a comparison result obtained by the second comparison section.

A data transfer control device for controlling mutual data transfer between first and second memory arrays based on an input control command, data transfer start addresses and a data transfer completion address of the first and second memory arrays, and the number of batches of data to be transferred, the device comprising:

• a command recognition section for recognizing the input control command:
• a second address output section for outputting a data transfer start address of the first memory array, the number of batches of data to be transferred, and a data transfer start address of the second memory array based on the input control command in this storage order or outputting the data transfer start address of the second memory array, the number of batches of data to be transferred, and a data transfer start address of the first memory array based on the input control command in this storage order;
• a first memory address storage section for storing the data transfer start address of the first memory array output from the second address output section;
• a first memory address counter section for incrementing a memory address for each unit of data transfer;
• a first memory address transfer section for transferring the data transfer start address from the first memory address storage section to the first memory address counter section;
• a second memory address storage section for storing the data transfer start address of the second memory array output from the second address section;
• a second memory address counter section for incrementing a memory address for each unit of data transfer;
• a second memory address transfer section for transferring the data transfer start address from the second memory address storage section to the second memory address counter section;
• a transfer data number storage section for storing the number of batches of data to be transferred output from the second address output section:
• a data counter section for incrementing the number of batches of data for each data transfer unit;
• a second comparison section for comparing the number of batches of data to a value of the data counter section;
• and
• a second data transfer control section performing the mutual data transfer between the first and second memory arrays based on address values set in the first and second memory address counter sections and completing the mutual data transfer based on a comparison result obtained by the second comparison section.