Fast accessible semiconductor memory device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsShigeki Tomishima, Tsukasa Ooishi, Hiroshi Kato
Life of this patent
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Abstract
A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.
Claims5
A semiconductor memory device, comprising:
- a plurality of banks each having a plurality of memory cells arranged in a matrix of rows and columns and having a memory cell row driven into a selected state independently of each other, each of said plurality of banks being divided into a plurality of sub banks;
- a plurality of internal data lines arranged extending over said plurality of banks in the column direction;
- sub bank selection circuitry for connecting a memory cell column of an addressed sub bank in an addressed bank to said plurality of internal data lines in parallel in accordance with a bank/sub bank address signal identifying a bank and a sub bank;
- a plurality of write/read circuits provided corresponding to said plurality of internal data lines and divided into a plurality of groups, for transferring data with corresponding internal data lines upon activation thereof;
- and
- a data selection circuit for selecting a write/read circuit of a designated group from said plurality of write/read circuits for connection to global data bus in accordance with a group address signal.
Dependencies are inferred from the claim text.