Apparatus for operating an integrated circuit having a sleep mode

A refresh controller for use in an integrated circuit having a memory comprising a plurality of dynamic memory cells arranged in a plane of rows and columns, the refresh controller comprising:

• a row refresh circuit connected to the memory to refresh a selected row of memory cells;
• and
• a row select circuit connected to the row refresh circuit to select a first row of the memory to be refreshed, and then select a second row of the memory to be refreshed, wherein the first and second rows may be any two rows of the memory.

A programmable data processor for operating a memory comprising a plurality of dynamic memory cells arranged in a plane of rows and columns, the processor comprising:

• row refresh means connected to the memory to refresh a selected row of memory cells;
• and
• row select means connected to the row refresh circuit to select a first row of the memory to be refreshed, and then select a second row of the memory to be refreshed, wherein said first and second rows may be any two rows of the memory.