Static memory having self-timing circuit
AssigneeFujitsu Limited
InventorTsuyoshi Kodama
Life of this patent
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Abstract
A static memory including a memory cell array having word lines, bit line pairs, and memory cells, each having a pair of nodes holding opposite levels; includes a dummy circuit disposed along the memory cell array, having a dummy word line, a dummy bit line pair, a self-timing dummy memory cell connected to the dummy word and bit lines and having a pair of nodes holding opposite levels, and load dummy memory cells connected to the dummy bit line pair; and a timing control circuit for detecting a voltage change of the dummy bit line pair to generate a start signal to a sense amplifier. The pair of nodes of the self-timing dummy memory cell are fixed to a first status, and the pair of nodes of the load dummy memory cell are fixed to a second status opposite to first status.
Claims8
A static memory comprising:
- a memory cell array having a plurality of word lines, a plurality of bit line pairs, and memory cells, disposed at cross sections thereof, each having a pair of nodes which hold opposite levels;
- a dummy circuit disposed along the memory cell array, having a dummy word line, a dummy bit line pair, a plurality of self-timing dummy memory cells which are connected to the dummy word line and dummy bit line pair and have a pair of nodes holding opposite levels, and a plurality of load dummy memory cells connected to the dummy bit line pair, wherein said plurality of self-timing dummy memory cells drives the bit line together in response to a selection of dummy word line;
- and
- a timing control circuit for detecting a voltage change of the dummy bit line pair to generate a timing control signal,
- wherein one of the pair of nodes of the self-timing dummy memory cells are connected to a higher level so as to be fixed to a first status, and one of the pair of nodes of all of the load dummy memory cell are connected to a around level so as to be fixed to a second status opposite to the first status.
A static memory:
- a memory cell array having a plurality of word lines, a plurality of bit line pairs, and memory cells, disposed at cross sections thereof, each having a pair of nodes which hold opposite levels;
- a dummy circuit disposed along the memory cell array, having a dummy word line, a dummy bit line, a plurality of self-timing dummy memory cells which are connected to the dummy word line and dummy bit line and have a pair of nodes holding opposite levels, and a plurality of load dummy memory cells connected to the dummy bit line pair, wherein said plurality of self-timing dummy memory cells drives the bit line together in response to a selection of dummy word line;
- and
- a timing control circuit for detecting a voltage chance of the dummy bit line to generate a timing control signal,
- wherein the pair of nodes of the self-timing dummy memory cells are fixed to a first status, and the pair of nodes of some of the load dummy memory cell are fixed to a second status opposite to the first status and the remaining ones are fixed to the same status as that of the self-timing dummy memory cells.
Dependencies are inferred from the claim text.