Integrated clock generator, particularly for driving a semiconductor memory with a test signal

In combination with a semiconductor memory, an integrated clock generator for driving the semiconductor memory with a test signal, the integrated clock generator comprising:

• an input/output interface for inputting or outputting data to or from the integrated clock generator;
• a clock source outputting a reference signal;
• a delay locked loop having a first input coupled to said input/output interface for receiving an input signal from said input/output interface, said delay locked loop having a second input coupled to said clock source and receiving the reference signal, said delay locked loop having an output providing an output clock signal based on the input signal and the reference signal and coupled to said input/output interface;
• a selection circuit coupled to said delay locked loop for changing over from a first, synchronizing mode of operation to a second, freewheeling mode of operation;
• and
• an adder/subtractor coupled to said delay locked loop for providing a settable delay between the input signal and the reference signal in the second, freewheeling mode of operation.