Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsAkihito Hamamatsu, Shinji Tanaka
Life of this patent
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Abstract
A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.
Claims20
A semiconductor memory device comprising:
- a power supply terminal for receiving a power supply voltage;
- a memory cell array including a plurality of memory cells;
- a peripheral circuit for inputting and outputting data to and from said plurality of memory cells;
- and
- a test mode circuit for operating, in an operation of shifting to a test mode, to detect a voltage level of a power supply voltage supplied from said power supply terminal in response to external input of a test mode shift signal, and generate a test mode signal for testing a special operation when the detected voltage level is different from the voltage level in a normal operation, wherein
- said peripheral circuit performs input and output of data used for testing said special operation of each of said plurality of memory cells in response to said test mode signal.
A semiconductor memory device comprising:
- a power supply terminal for receiving a power supply voltage;
- a memory cell array including a plurality of memory cells;
- a peripheral circuit for inputting and outputting data to and from each of said plurality of memory cells;
- and
- a test mode circuit for operating, in an operation of shifting to a test mode, to produce a plurality of logic signals based on said power supply voltage, and to output said plurality of produced logic signals as test signals indicating contents of the test for said memory cell, wherein
- said peripheral circuit performs input and output of data used for executing the test corresponding to a logical pattern of said plurality of logic signals.
A semiconductor module comprising:
- a PLL circuit for generating a clock signal formed of a predetermined frequency;
- a registered buffer circuit for converting an externally supplied input signal to an input signal formed of a voltage level for internal use, and outputting the converted input signal in synchronization with the clock signal;
- a power supply terminal for receiving a power supply voltage;
- and
- a plurality of semiconductor memory devices for receiving said input signal from said registered buffer circuit and operating in synchronization with said clock signal, wherein
- each of said plurality of semiconductor memory devices includes:
- a memory cell array including a plurality of memory cells,
- a peripheral circuit inputting/outputting of data to and from each of said plurality of memory cells, and
- a test mode circuit detecting, in an operation of shifting to a test mode, the voltage level of the power supply voltage supplied from said power supply terminal in response to input of a test mode shift signal from said registered buffer circuit, and generating a test mode signal for testing a special operation based on the detected voltage level;
- and
- said peripheral circuit performs input/output of data used for testing said special operation to and from each of said plurality of memory cells in response to said test mode signal.
Dependencies are inferred from the claim text.