Semiconductor memory device for reducing number of input cycles for inputting test pattern

A memory device comprising:

• a memory cell array including a plurality of memory cells;
• an I/O buffer;
• an address providing unit responsive to a test mode signal for providing an address, wherein said address providing unit initializes said address to an initial address before an access to said memory cell array, and increments said address from initial address during said access;
• and
• an address decoder which allows said memory cell array to be accessed in response to said address,
• wherein said address providing unit, when said test mode signal is activated, fixes said initial address to a predetermined initial address, and
• wherein said address providing unit, when said test mode signal is not activated, receives an external initial address through said I/O buffer to set said initial address to be said external initial address.

A method of operating a memory device comprising:

• providing a test mode signal;
• providing a command which controls an access to a memory cell, wherein said providing said command includes:
• setting said command to be a predetermined internal command when said test mode signal is activated, and
• setting said command to be an external command received from an external circuit when said test mode signal is not activated;
• providing an address in response to said command;
• and
• allowing said memory cell array to be accessed in response to said address.

A method of operating a memory device comprising:

• providing a test mode signal;
• providing an address for an access to a memory cell array;
• allowing said memory cell array to be accessed in response to said address, wherein said providing said address includes:
• initializing said address to a predetermined initial address before said access when said test mode signal is activated;
• initializing said address to an external initial address received from an external circuit before said access when said test mode signal is not activated;
• increasing said address during said access.