Semiconductor device
AssigneeHitachi, Ltd.
InventorTakeshi Sakata
Life of this patent
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Abstract
In the conventional column-side block redundancy for DRAM, competition for the replacing regions occurs unless a repair address of a large number of bits is stored in order to replace with a small replacement unit. According to one aspect of the invention, replacement decision is performed in order that a second replacement region can be made smaller than a first replacement and that the second replacement is given priority over the first replacement. Therefore, the first replacement can be controlled by a repair address of a small number of bits, thus making it possible to achieve a semiconductor device having a defect repair circuit with small area and high repair efficiency.
Claims8
A semiconductor memory device comprising:
- a first cell array comprising a plurality of memory cells provided at the intersection of a plurality of word lines and a plurality of bit lines;
- a second cell array for, when said first cell array includes first and second defects, replacing said first and second defects;
- and
- a repair decision circuit comprising a first row address comparator for storing (n−q1) bits of address and outputs a first decision result, a second row address comparator for storing (n−q2) bits of address and outputs a second decision result, and a selection circuit coupled to said first and second row address comparators,
- wherein said repair decision circuit outputs replacing information for replacing said first and second defects in (n−q1) bit region by comparing (n−q1) bits of row address with address stored in said first row address comparator and comparing (n−q2) bits of row address with address stored in said second row address comparator,
- wherein said second defect is given priority to be replaced over said first defect;
- and
- wherein q1 is larger than q2.
A semiconductor memory device comprising:
- a plurality of first memory cells coupled to first word lines and first bit lines;
- a plurality of second and third memory cells for replacing said first memory cells;
- a first row address comparator comprising a first input node for inputting (n−q1) bits of address, a first address storage means for storing (n−q1) bits of repair address, and a first output node for outputting a first decision result when address inputted in said first input node matches address in said first address storage means;
- a second row address comparator comprising a second input node for inputting (n−q2) bits of address, a second address storage means for storing (n−q2) bits of repair address, and a second output node for outputting a second decision result when address inputted in said second input node matches address in said second address storage means;
- and
- a selection circuit coupled to said first and second output nodes,
- wherein said selection circuit outputs first selection result for selecting said second memory cells when said first decision result is inputted, and outputs second selection result for selecting said third memory cells when said second decision result is inputted, and outputs said second selection result when said first and second decision results are inputted, and
- wherein q1 is larger than q2.
Dependencies are inferred from the claim text.