Method and system for discharging the bit lines of a memory cell array after erase operation

A method for use in erasing data stored in a memory cell, comprising:

• asserting a voltage differential across a tank region and a gate region of the memory cell, wherein the tank region has a first conductivity type and the tank region is located within a well region of a second conductivity type;
• floating the voltage of a source region and drain region of the memory cell, wherein the source and drain region are located within the tank region and comprise a material having the second conductivity type;
• discharging a charge stored in the drain region by:
• floating the tank region;
• floating the well region;
• electrically connecting the source region to a first electric potential lower than the potential of the drain region;
• and
• electrically connecting the well region and the tank region to a second electric potential lower than both the existing electric potential of the well region and the existing electric potential of the tank region.