Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics

Abstract

A semiconductor memory device includes a plurality of word lines and a plurality of bit lines. A plurality of memory cells, each formed of a MIS transistor, are disposed at intersections of the word lines and the bit lines. The threshold voltages of the MIS transistors being externally electrically controllable according to charges to be injected to floating gates thereof. The floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells. A first row decoder applies a normal voltage to a selected word line to select memory cells connected to the selected word line, when reading data. A second row decoder applies a predetermined source voltage to sources of memory cells connected to the selected word line, and applies an unselected state establishing voltage to the sources of memory cells, including those overerased by the collective erasing, connected to unselected word lines, when reading data.

Dependencies are inferred from the claim text.