Semiconductor level shifter circuit
AssigneeNEC Electronics Corporation
InventorsTakayuki Kurokawa, Hiroshi Sugawara
Life of this patent
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Abstract
A level shifter (1) that may provide a relatively high-speed operation in a level shifting mode and a non-level shifting mode has been disclosed. Level shifter (1) may include a transistor (P101) providing a controllable current path between a voltage terminal (3) and an output signal (TOUT) based on the logic level of an input signal (IN). Series connected transistors (P104 and P105) may provide a controllable current path between voltage terminal (3) and output signal (TOUT) based on the logic level of an input signal (IN). Transistor (P105) may be enabled in a Vcc mode and may be disabled in a Vpp mode. In this way, an equivalent transistor width (WT) may be adjusted in accordance with a mode of operation and a transition time of output signal (TOUT) may be improved.
Claims20
A level shifter, comprising:
- a first drive circuit coupled between a first power supply terminal and a first output node;
- a second drive circuit coupled between the first power supply terminal and a second output node;
- a third drive circuit coupled between a reference potential and the first output node;
- a fourth drive circuit coupled between the reference potential and the second output node;
- and
- the first drive circuit having a first effective drive circuit width and the second drive circuit having a second effective drive circuit width wherein the first and second effective drive circuit widths are adjusted in accordance with a voltage level of the first power supply terminal.
A level shifter, comprising:
- a first drive current path coupled between a power supply node and an output node;
- a second drive current path coupled between the power supply node and the output node wherein
- the second drive current path is enabled when the power supply node is at a first potential and disabled when the power supply node is at a second potential.
A semiconductor device, comprising:
- a first mode of operation where a first power supply potential is supplied to a power supply terminal and a second mode of operation where a second power supply potential is supplied to the power supply terminal;
- a level shifter providing a shift between the first power supply potential and the second power supply potential in the first mode of operation, the level shifter including
- a first drive circuit coupled to provide a first current path between the power supply terminal and a first output node in response to a first logic level of an input signal;
- and
- a second drive circuit coupled to provide a second current path between the power supply terminal and the first output node in response to the first logic level of the input signal when in the second mode of operation and provide a high impedance path between the power supply terminal and the first output node in the first mode of operation.
Dependencies are inferred from the claim text.