Flash memory array architecture having staggered metal lines
AssigneeAdvanced Micro Devices, Inc.
InventorsSameer Haddad, Richard Fastow
Life of this patent
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Abstract
A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.
Claims13
A memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of elongated, substantially straight source/drain regions, each comprising alternating sources and drains along its length;
- at least one bit line being connected to two source/drain regions in alternate manner along the bit line length.
A memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of elongated source/drain regions, each comprising alternating sources and drains along its length;
- each bit line being made up of the plurality of segments, each segment being non-aligned with an adjacent segment, each bit line being connected to two source/drain regions in alternate manner along the bit line length.
Dependencies are inferred from the claim text.