Memory cell, nonvolatile memory device and control method therefor improving reliability under low power supply voltage

A memory cell comprising:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and
• a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• storing operation of the memory cell is carried out by swinging the voltage of the plate line between power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the pair of switching elements in off states.

A memory cell comprising:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and
• a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• storing operation of the memory cell is carried out by swinging the voltage of the plate line between a first voltage that is higher than power supply voltage of the memory cell and the ground potential while keeping the pair of switching elements in off states.

A memory cell comprising:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and
• a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• recall operation of the memory cell is carried out by driving the plate line to a third voltage that is higher than power supply voltage of the memory cell and thereafter raising supply voltage of the memory cell from the ground potential to the power supply voltage of the memory cell while keeping the pair of switching elements in off states.

A memory cell comprising:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and
• a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• recall operation of the memory cell is carried out by driving the plate line to a fourth voltage that is lower than the ground potential and raising supply voltage of the memory cell from the ground potential to the power supply voltage of the memory cell while keeping the pair of switching elements in off states.

A nonvolatile memory device comprising memory cells that are arranged in a matrix, wherein:

• the memory cell includes:
• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, and
• at least storing operation or recall operation of each memory cell is carried out according to operation selected from:
• (A) first storing operation in which the voltage of the plate line is swung between a first voltage that is higher than power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the pair of switching elements in off states;
• (B) second storing operation in which the voltage of the plate line is swung between the power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the pair of switching elements in off states;
• (C) third storing operation in which the voltage of the plate line is swung between a first voltage that is higher than the power supply voltage of the memory cell and the ground potential while keeping the pair of switching elements in off states;
• (D) first recall operation in which the plate line is driven to a third voltage that is higher than power supply voltage of the memory cell and thereafter supply voltage of the memory cell is raised from the ground potential to the power supply voltage of the memory cell while keeping the pair of switching elements in off states;
• and
• (E) second recall operation in which the plate line is driven to a fourth voltage that is lower than the ground potential and supply voltage of the memory cell is raised from the ground potential to the power supply voltage of the memory cell while keeping the pair of switching elements in off states.

A control method for a memory cell that comprises:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• storing operation of the memory cell is carried out by swinging the voltage of the plate line between a first voltage that is higher than power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the pair of switching elements in off states.

A control method for a memory cell that comprises:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• storing operation of the memory cell is carried out by swinging the voltage of the plate line between power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the pair of switching elements in off states.

A control method for a memory cell that comprises:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• storing operation of the memory cell is carried out by swinging the voltage of the plate line between a first voltage that is higher than power supply voltage of the memory cell and the ground potential while keeping the pair of switching elements in off states.

A control method for a memory cell that comprises:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• recall operation of the memory cell is carried out by driving the plate line to a third voltage that is higher than power supply voltage of the memory cell and thereafter raising supply voltage of the memory cell from the ground potential to the power supply voltage of the memory cell while keeping the pair of switching elements in off states.

A control method for a memory cell that comprises:

• a pair of memory nodes for holding a pair of complementary voltages;
• a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line;
• and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, wherein:
• recall operation of the memory cell is carried out by driving the plate line to a fourth voltage that is lower than the ground potential and raising supply voltage of the memory cell from the ground potential to the power supply voltage of the memory cell while keeping the pair of switching elements in off states.