Ferroelectric memory input/output apparatus
AssigneeIntel Corporation
InventorDavid GenLong Chow
Life of this patent
Estimating the term…
Abstract
A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.
Claims13
A memory system, comprising:
- at least two ferroelectric memory devices arranged sequentially, wherein:
- each memory device has a data in control signal line, a data out control signal line, and a busy signal line;
- the data out control signal line of each memory device is electrically connected to the data in control signal line of a next device in sequence, terminating with a last device;
- a system controller to generate an initial data in control signal for a first memory device;
- a data bus to transfer data between each memory device and the system controller;
- and
- an address bus to provide addressing of the memory devices.
A method of performing a read operation on at least two ferroelectric memory devices linked sequentially, the method comprising:
- transmitting an address to the ferroelectric memory devices;
- detecting a busy signal from the ferroelectric memory devices;
- asserting a data in control signal for a selected one of the memory devices;
- receiving data from the selected one of the memory devices, until all data has been received from the selected one;
- asserting a data out control signal from the selected one, wherein a line upon which the data out control signal is asserted from the selected one is electrically connected to a line upon which a data in control signal is asserted for a next memory device;
- repeating the receiving and asserting processes until all data has been received from all devices.
A method of performing a write operation on at least two ferroelectric memory devices linked sequentially, the method comprising:
- receiving a data in control signal from a system controller, indicating that data is available to be written to a selected one of the memory devices;
- receiving data from the system controller at the selected one;
- asserting a busy signal;
- asserting a data out control signal, indicating that the selected one of the devices has completed the write operation for that device;
- and
- receiving data from the system controller at each of the memory devices until all memory arrays have received their data.
A memory device, comprising:
- a ferroelectric polymer memory array;
- an address latch, operable to temporarily store addresses for memory operations;
- a data latch, operable to temporarily store data;
- and
- device control circuitry operable to:
- receive and send control signals, external to the memory device, such that a serial data out signal is transmitted to an adjacent memory device as a serial data in signal, the control signals including a busy signal receivable from the ferroelectric polymer memory array;
- direct the address latch to receive address signals;
- and
- direct the data latch to receive and send data signals.
Dependencies are inferred from the claim text.