Inrush current suppression circuit

An inrush current suppression circuit installed between a DC voltage and a load with a parallel system capacitor comprising:

• a first current limiting circuit comprising:
• a first resistor;
• a first controlled switch;
• and
• a second controlled switch wherein said first controlled switch and said first resistor are electrically connected in series, and said second controlled switch is electrically connected in parallel to said first controlled switch and said first resistor;
• and
• a second current limiting circuit comprising:
• a second resistor;
• a third controlled switch;
• and
• an energy-storing capacitor wherein said second resistor and said energy-storing capacitor are electrically connected in series, said second resistor is electrically connected in parallel to said third controlled switch, said second current limiting circuit is electrically connected in parallel to said system capacitor, and said first current limiting circuit is electrically connected with said DC voltage and said second current limiting circuit,
• whereby, when said DC voltage is detected, the first controlled switch is conducted;
• when a voltage of two ends of said load reaches a first threshold value, said second controlled switch is soft turned-on so as to bypass said first resistor;
• and when a voltage of said energy-storing capacitor reaches a second threshold value, said third controlled switch is soft turned-on so as to bypass said second resistor.