Memory system having programmable multiple and continuous memory regions and method of use thereof

A memory sub-system for a graphics processing system, comprising:

• first and second addressable memory regions;
• a register to store values defining first and second portions of a first memory space and first and second portions of a second memory space, and an offset value for each memory space;
• and
• a memory controller coupled to the register and to the first and second addressable memory regions, the memory controller adapted to access the first and second addressable memory regions and in response to receiving a requested memory address corresponding to a logical memory address in the second portion of the first or second memory spaces, add the respective offset value to the requested memory address and access the resulting memory location.

A memory system for storing graphics data in a computer graphics processing system, comprising:

• a plurality of memory arrays having memory locations corresponding to memory addresses;
• a register to store values defining allocation of the plurality of memory arrays to first and second portions of a first memory space and first and second portions of a second memory space, the register further storing an offset value for each memory space;
• and
• a plurality of memory controllers corresponding to the plurality of memory arrays, each memory controller coupled to a memory controller bus on which memory addresses can be passed from one memory controller to the other and coupled to query the register for the stored values, each memory controller further coupled to a respective memory array and adapted to add in response to receiving a requested memory address corresponding to a logical memory address in the second portion of the first or second memory spaces a respective offset value to the requested memory address and provide the resulting address to the memory controller coupled to the memory array including the memory location corresponding to the resulting address.

A graphics processing system, comprising:

• a bus interface for coupling to a system bus;
• a graphics processor coupled to the bus interface to process graphics data;
• address and data busses coupled to the graphics processor to transfer address and graphics data to and from the graphics processor;
• display logic coupled to the data bus to drive a display;
• a memory request bus coupled to the data bus to drive a display;
• access requests;
• and
• a memory system coupled to the data bus to store and retrieve data, the memory system comprising:
• first and second addressable memory regions;
• and
• a memory controller coupled to the first and second addressable memory regions and having a register to store for first and second logical memory spaces a respective offset value and values defining first and second portions for the respective memory space, the memory controller adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.

A computer system, comprising:

• a system processor;
• a system bus coupled to the system processor;
• a system memory coupled to the system bus;
• and
• a graphics processing system coupled to the system bus, the graphics processing system, comprising:
• a bus interface for coupling to the system us;
• a graphics processor coupled to the bus interface to process graphics data;
• address and data busses coupled to th graphics processor to transfer address and graphics data to and from the graphics processor;
• display logic coupled to the data bus to drive a display;
• a memory request bus coupled to the graphics processor to transfer memory access requests;
• and
• a memory system coupled to the data bus to store and retrieve data, the memory system comprising:
• first and second addressable memory regions;
• and
• a memory controller coupled to he first and second addressable memory regions and having a register to store for first and second logical memory spaces a respective offset value and values defining first and second portions for the respective memory space, the memory controller adapted to access the first addressable memory region in response to receiving a memory address for a location within the first portions of the first and second memory spaces and to access the second addressable memory region in response to receiving a memory address for a location within the second portions of the first and second memory spaces.