Liquid crystal display control device, liquid crystal display device using the same, and information processor

A display device for displaying a video signal, comprising:

• a display unit for displaying said video signal;
• a clock generation circuit for generating a 1/n-frequency dot clock signal having a period that is n times a horizontal synchronous signal of said video signal;
• a synchronous signal generation circuit for inverting a logical level of said 1/n-frequency dot clock signal in accordance with a vertical synchronous signal of said video signal;
• a memory for storing said video signal;
• and
• a control circuit for writing said video signal into said memory in accordance with said 1/n-frequency dot clock signal and for reading said video signal from said memory in accordance with an output synchronous signal that is different from said 1/n-frequency dot clock signal to output the video signal to said display unit.

A display device for displaying a video signal comprising:

• a display unit for displaying said video signal;
• a synchronous signal generation circuit for generating a 1/n-frequency dot clock signal by dividing frequency of a dot clock externally inputted by n, and for controlling a phase of said 1/n-frequency dot clock signal in accordance with a frame period of said video signal;
• a memory for storing said video signal;
• and
• a control circuit for writing said video signal into said memory in accordance with said 1/n-frequency dot clock signal and for reading said video signal from said memory in accordance with an output synchronous signal that is different from said 1/n-frequency dot clock signal to output the video signal to said display unit.

A display device for displaying a video signal comprising:

• a display unit for displaying said video signal;
• a synchronous signal generation circuit for generating 1/n-frequency dot clock signal by dividing frequency of a dot clock externally inputted by n, and for inverting a phase of said 1/n-frequency dot clock signal in accordance with a vertical synchronous signal of said video signal;
• a memory for storing said video signal;
• and
• a control circuit for writing said video signal into said memory in accordance with said 1/n-frequency dot clock signal and for reading said video signal from said memory in accordance with an output synchronous signal that is different from said 1/n-frequency dot clock signal to output the video signal to said display unit.