Self timed pre-charged address compare logic circuit

A self timed address compare circuit for comparing plural bit addresses, comprising:

• an address input HIT clock circuit for providing a self-timed clock signal in response to the arrival of input data having a bit from each address input to the input HIT clock circuit, and
• a bit compare circuit activated upon the arrival of incoming addresses to be compared and comparing bits of said addresses, and
• a compare evaluation circuit for timing of a HIT evaluation clock signal,
• and a receiver for receiving an output of said compare evaluation circuit, whereby
• data clocking is reliably self-timed in response to the arrival of the input data insuring proper compare timing upon the arrival of the incoming addresses being compared by said bit compare circuit to generate an accurate internal HIT evaluation clock signal generated by the rising edges of the input data by said evaluation clock circuit.