Self-bias and differential structure based PLL with fast lockup circuit and current range calibration for process variation

A phase locked loop (PLL) method for controlling a voltage controlled differential oscillator to generate an output frequency signal which is a selected multiple of an input reference signal comprising:

• increasing or decreasing said output frequency signal from the oscillator at a relatively high frequency response towards the selected multiple of the reference signal;
• detecting a phase shift between said reference signal and said output frequency signal and producing an error signal;
• detecting when said output frequency signal passes said selected multiple of said reference signal;
• and
• increasing and decreasing said output frequency signal at a reduced frequency response when the reference signal passage is detected before the PLL achieves a lock state.

A method of adjusting a bias current output by a bias generator used in a phase locked loop to control a differential oscillator, such that said differential oscillator output frequency signal is a selected multiple of an input reference signal, said method comprising the steps of:

• controlling the bias generator, by switching in or out any of a plurality of current generators in response to a binary switch signal;
• monitoring a bias generator input voltage;
• comparing said input voltage to a reference voltage;
• incrementing said binary switching signal in response to said comparison to identify an optimal bias current;
• and
• maintaining the optimal bias current until the PLL is reset.