Complementary pass transistor based flip-flop
AssigneeSamsung Electronics Co., Ltd.
InventorsKi-tae Park, Hyo-sik Won
Life of this patent
Estimating the term…
Abstract
A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.
Claims26
A complementary pass transistor based flip-flop comprising:
- a first virtual power supply unit for providing a first virtual power supply voltage by receiving a first power supply voltage having a highest voltage level;
- a second virtual power supply unit for providing a second virtual power supply voltage by receiving a second power supply voltage having a lowest voltage level;
- a clock delay unit for receiving and outputting a clock signal by inverting and delaying the clock signal, and further receiving at least one control signal and outputting the clock signal by inverting and delaying the clock signal in response to the control signal;
- a switch unit for switching input data in response to the clock signal and an output signal of the clock delay unit;
- and
- a latch unit for latching at least one output signal of the switch unit,
- wherein both the clock delay unit and the switch unit comprise low-threshold MOS transistors, the latch unit comprises a plurality of low-threshold MOS transistors or comprises a plurality of low-threshold MOS transistors and at least one high-threshold MOS transistor, the plurality of low-threshold MOS transistors each having a lower threshold voltage than the high-threshold MOS transistor and being operated between the first power supply voltage and the second power supply voltage, between the first power supply voltage and the second virtual power supply voltage, between the first virtual power supply voltage and the second power supply voltage, or between the first virtual power supply voltage and the second virtual power supply voltage, and the high-threshold MOS transistor being operated between the first power supply voltage and the second power supply voltage.
Dependencies are inferred from the claim text.