Method and system for reducing hazards in a flip-flop
AssigneeFujitsu Limited
InventorsNikola Nedovic, Vojin G. Oklobd{haeck over (z)}ija, William W. Walker
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Abstract
The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit. In an embodiment of the present invention a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
Claims34
A method for reducing hazards in a flip-flop, comprising, a pro-charged stage coupled to an evaluation stage by at least an internal node, said method comprising the steps of:
- said pro-charged stage charging said internal node, and thereafter setting said internal node based on a data input in response to a transition in a clock signal;
- preventing said evaluation stage from evaluating said internal node for a predetermined time period after the transition in the clock signal, said preventing step comprising the step of delaying the turn on of a transistor in the evaluation stage during the predetermined time period;
- and
- after said predetermined time period, evaluating said internal node by said evaluation stage to determine an output of said flip-flop.
A system for reducing hazards in a hybrid flip-flop comprising:
- a pre-charge stage for charging a pre-charge stage output and thereafter setting the pre-charge stage output depending upon a data input during a transparency window;
- and
- an evaluation stage for evaluating said pre-charge stage output to produce a data output during said transparency window, wherein said evaluation stage is enabled to change said data output to a low logic level only after a predetermined time period from the beginning of the transparency window, wherein said pre-charge stage sets said pre-charge stage output during said predetermined time period, and wherein the evaluation stage is enabled to change said data output to a low logic level by at least the turning on of a transistor in the evaluation state at the end of the predetermined time period.
A system for reducing hazards in a hybrid flip-flop comprising:
- a pre-charge stage for charging a pro-charge stage output and thereafter setting the pro-charge stage output depending upon a data input during a transparency window;
- and
- an evaluation stage for evaluating said pro-charge stage output to produce a data output during said transparency window, wherein said evaluation stage is enabled to change said data output after a predetermined time period from the beginning of the transparency window, wherein said pro-charge stage sets said pro-charge stage output during said predetermined time period, and wherein the evaluation stage is enabled to change said data output by at least the turning on of a transistor in the evaluation state at the end of the predetermined time period.
A method for reducing hazards in a flip-flop, comprising, a pro-charged stage coupled to an evaluation stage by at least an internal node, said method comprising the steps of:
- charging the internal node and thereafter setting a first logic level for the internal node based on a data input to said pre-charged stage within a first section of a transparency window;
- disabling, for a predetermined time period from the beginning of the transparency window, said evaluation stage from setting a data output to a second logic level during said first section of said transparency window, said disabling step comprising the step of delaying the turn on of a transistor in the evaluation stage during the predetermined time period;
- and
- determining said data output during a second section of said transparency window based on said first logic level, wherein said second section follows said first section.
A method for reducing power consumption in a hybrid flip-flop, comprising, a pro-charged stage coupled to an evaluation stage by at least an internal node, said method comprising the steps of:
- pre-charging the internal node;
- setting an input of said pro-charged stage to a first high logic level, wherein an output of said evaluation stage has a second high logic level;
- responsive to said setting said input, setting said pre-charged internal node to a low logic level within a beginning part of a transparency window;
- disabling, for a predetermined time period during said beginning part of said transparency window, said evaluation stage from setting said output to a low logic level, said disabling step comprising the step of delaying the turn on of a transistor in the evaluation stage during the predetermined time period;
- and
- said evaluation stage maintaining said second high logic level on said output during a remainder of said transparency window, using said low logic level of said internal node.
A system for reducing hazards in a hybrid flip-flop comprising:
- a pre-charge stage for charging a pre-charge stage output and thereafter setting the pre-charge stage output depending upon a data input during a first part of a transparency window, said pre-charge stage comprising a first conditional keeper for keeping said pre-charge stage output;
- and
- an evaluation stage for evaluating said pre-charge stage output, after a predetermined time period from the beginning of the transparency window, to produce a data output during a second part of said transparency window, wherein the evaluation stage is enabled to evaluate said pre-charge stage output by at least the turning on of a transistor in the evaluation state at the end of the predetermined time period, said evaluation stage comprising a second conditional keeper for keeping said data output.
A system for reducing hazards in a hybrid flip-flop comprising:
- a first means for charging a pre-charge stage output and thereafter setting the pre-charge stage output depending upon a data input during a first part of a transparency window, said pre-charge stage comprising a first conditional keeper means for keeping said pre-charge stage output;
- and
- a second means for evaluating said pre-charge stage output, after a predetermined time period from the beginning of the transparency window, to produce a data output during a second part of said transparency window, said second means being enabled to evaluate said pre-charge stage output by at least the turning on of a transistor of the second means at the end of the predetermined time period, and said second means comprising a second conditional keeper means for keeping said data output.
Dependencies are inferred from the claim text.