PLL circuit including a control logic circuit for adjusting the delay times of the clocks so that the phase error of the clocks is reduced

A PLL circuit comprising:

• first delay means for delaying a reference clock by a first delay time to obtain a delayed reference clock;
• second delay means for delaying a return clock by a second delay time to obtain a delayed return clock;
• a PLL part for receiving said delayed reference clock and said delayed return clock and outputting a PLL output so that phases of the delayed reference and delayed return clocks are synchronous with each other, a signal in association with said PLL output being returned as said return clock;
• and
• phase difference reducing delay control means for performing a delay means controlling process based on said reference clock and said return clock, said delay means control process changing at least one of said first and second delay time so that a phase difference between said reference clock and said return clock is reduced,
• wherein said phase difference reducing delay controlling means includes:
• phase comparing means for comparing phases of said reference clock and said return clock to output a phase comparison signal;
• and
• delay controlling means for performing said delay means controlling process wherein a degree of advance in phase of said return clock with respect to said reference clock is determined based on said phase comparison signal, and a first and a second delay control signals are outputted to said first and second delay means, the first and the second delay control signals being such that the instruction contents thereof change in such a direction that a relative delay time of said second delay time to said first delay time increases when a phase advance determination representing that said return clock advances in phase is made, and in such a direction that said relative delay time decreases when a phase delay determination representing that said return clock delays in phase is made, and
• wherein said second delay means includes:
• a delay line for inputting said return clock at an input end, allowing the return clock to transmit therethrough and outputting the return clock as said delayed return clock from an output end;
• and
• capacity value changing means connected to said delay line, a capacity value thereof associated with said delay line being changed based on said second delay control signal.