Output buffer circuit for reducing variation of slew rate due to variation of PVT and load capacitance of output terminal, and semiconductor device including the same

A semiconductor device comprising:

• a PLL circuit including a voltage controlled oscillator that outputs a first bias voltage and a second bias voltage;
• a slew rate control circuit controlled by the first bias voltage and the second bias voltage, for controlling the voltage of a pull-up signal in multiple stages in response to a first control signal and controlling the voltage of a pull-down signal in multiple stages in response to a second control signal;
• and
• an output driver for pulling up the output terminal in response to the pull-up signal and pulling down the output terminal in response to the pull-down signal.

An output buffer circuit for a semiconductor device comprising:

• a pull-up driver for pulling up an output terminal in response to a pull-up signal;
• a pull-down driver for pulling down the output terminal in response to a pull-down signal;
• a first slew rate control circuit for controlling the voltage of the pull-up signal in multiple stages in response to a first control signal, the first slew rate control circuit comprising:
• a first delay circuit for delaying the first control signal in response to a first bias voltage and a second bias voltage;
• and
• a first control circuit for controlling the pull-up signal in response to the first control signal and the second bias voltage in a first stage of the multiple stages, and again controlling the pull-up signal in response to the first control signal and the output signal of the first delay circuit in a second stage of the multiple stages;
• and
• a second slew rate control circuit for pulling up the voltage of the pull-down signal in multiple stages in response to a second control signal.