Glitchless clock output circuit and the method for the same
AssigneeVIA Technologies, Inc.
InventorsChih Hsien Weng, Cheng-Yuan Wu, Chen-Hua Hsi
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Abstract
A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.
Claims16
A glitchless clock output circuit, which comprises:
- a selection circuit, which generates a plurality of select signals according to an input signal;
- a plurality of delay switching circuits, each of which receives the select signal and a corresponding delayed clock signal and generates a select enabling signal such that the transition of the select enabling signal is synchronized with the transition of the corresponding delayed clock signal;
- and
- an adaptive clock router circuit for selecting one of the delayed clock signals as a clock output signal according to a plurality of select enabling signals,
- wherein the delay switching circuit comprises:
- a first AND gate for receiving the delayed clock signal and the select enabling signal;
- a first OR gate for receiving the delayed clock signal and the select signal enabling;
- a second AND gate for receiving the select signal and the output of the first OR gate;
- and
- a second OR gate for receiving the outputs of the first and second AND gates and outputting the select enabling signal.
A glitchless clock output circuit, comprising:
- a plurality of delayed clock signals, each of which has a predetermined delay time with another delayed clock signal of said delayed clock signals;
- a plurality of select signals respectively corresponding to the delayed clock signals;
- an adaptive clock router circuit for selecting one of the delayed clock signals as a clock output signal according to one of a plurality of select enabling signals;
- and
- a plurality of delay switching circuits for generating the select enabling signals, each delay switching circuit comprising:
- a first AND gate for receiving the delayed clock signal and the select enabling signal;
- a first OR gate for receiving the delayed clock signal and the select enabling signal;
- a second AND gate for receiving the select signal and the output of the first OR gate;
- and
- a second OR gate for receiving the outputs of the first and second AND gates and outputting the select enabling signal.
Dependencies are inferred from the claim text.