Clocked pass transistor and complementary pass transistor logic circuits
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A logic circuit and associated method are provided to improve the switching performance of integrated circuit devices. The logic circuit includes a pass transistor logic circuit, a CMOS transistor pair connected as an inverter and having an input coupled to the output of the pass transistor logic circuit, a clocking transistor coupled between the inverter and a potential terminal to selectively enable the inverter according to a first clocking signal, and a precharge transistor coupled between the inverter output and a potential terminal to precharge the inverter output low according to a second clocking signal.
Claims17
A memory system, comprising:
- at least one memory device for storing data,
- said memory device having at least one control logic circuit;
- at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal;
- at least one precharge transistor coupled to said inverter and configured to precharge said output of said inverter to a first logic state;
- and
- at least one clocking transistor coupled to said inverter and configured to selectively enable said output of said inverter.
A memory system, comprising:
- at least one memory device for storing data,
- said memory device having at least one control logic circuit;
- at least one inverter including a CMOS transistor pair having a gate of a first transistor coupled to a gate of a second transistor, said coupled gates being coupled to an output of said at least one control logic circuit, and a first source/drain region of said first transistor coupled to a first source/drain region of said second transistor, said coupled first source/drain regions being coupled to an output of said inverter, wherein a second source/drain region of said first transistor is coupled to a first potential terminal;
- at least one clocking transistor having a gate coupled to a first clocking signal, a first source/drain region coupled to a second potential terminal, and a second source/drain region coupled to a second source/drain region of said second transistor;
- and
- at least one precharge transistor having a gate coupled to a second clocking signal, a first source/drain region coupled to said second potential terminal, and a second source/drain region coupled to said output of said inverter.
Dependencies are inferred from the claim text.