Clock power reduction technique using multi-level voltage input clock driver

An integrated circuit, comprising:

• a first power supply path leading to a first voltage;
• a second power supply path leading to a second voltages, wherein the first voltage is greater than the second voltage;
• a power reduction signal to enable a reduction in power consumption on the integrated circuit;
• and
• a clock driver circuit, comprising:
• a clock path for carrying an output clock signal from the clock driver circuit,
• a selection circuit coupled to the clock path, wherein the selection circuit selects one of the first power supply path and the second power supply path based on the power reduction signal, and
• a drive circuit operatively coupled to the clock path, wherein the drive circuit drives the output clock signal on the clock path from the selected one of the first power supply path and the second power supply path.