Interface scheme for connecting a fixed circuitry block to a programmable logic core
AssigneeCypress Semiconductor Corporation
InventorsAlan J. Coppola, Joel Stanley, Steven J. E. Wilton
Life of this patent
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Abstract
A method and architecture for providing signal paths between a programmable logic core and a fixed function core comprising the steps of (a) coupling one or more first signals between the fixed function core and an interface block configured to couple the fixed function core and the programmable logic core and (b) coupling one or more second signals between the interface block and the programmable logic core.
Claims30
A method for providing signal paths between a programmable logic core and a fixed function core comprising the steps of:
- (A) coupling one or more first signals between the fixed function core and a first input/output of an interface block configured to couple the fixed function core and the programmable logic core;
- (B) coupling one or more second signals between a second input/output of the interface block and the programmable logic core;
- and
- (C) coupling a first multiplexer part to a buffer part and coupling the first multiplexer and buffer parts between the first input/output and the second input/output of the interface block, wherein said first multiplexer part is configured to multiplex an input of said first multiplexer part and one or more inputs to one or more second multiplexer parts.
An apparatus comprising:
- one or more -programmable logic cores;
- one or more fixed function cores;
- and
- an interface circuit (a) configured to couple said one or more programmable logic cores and said one or more fixed function cores and (b) comprising (i) a plurality of buffer parts coupled to a first input/output of said interface circuit and (ii) a plurality of multiplexer parts coupled between said plurality of buffer parts and a second input/output of said interface circuit, wherein each of said plurality of multiplexer parts is configured to multiplex an input signal of two or more of said plurality of multiplexer parts.
An architecture for a programmable logic device comprising:
- a programmable logic core;
- one or more fixed function cores;
- and
- one or more interface blocks (a) configured to couple said programmable logic core and said one or more fixed function cores and (b) comprising (i) a plurality of buffer parts coupled to a first input/output of said interface blocks and (ii) a plurality of multiplexer parts coupled between said plurality of buffer parts and a second input/output of said interface blocks, wherein each of said plurality of multiplexer parts is configured to multiplex input signals of two or more of said plurality of multiplexer parts.
Dependencies are inferred from the claim text.