Data hold circuit, a semiconductor device and a method of designing the same

A data hold circuit comprising:

• first and second flip-flop circuits using the same signal as an input, and acquiring input signals on the basis of the same clock signal or mutually different clock signals synchronized with each other;
• first and second logic circuits whose output changes in accordance with a normal change of the output signals of said first and second flip-flop circuits;
• a third flip-flop circuit using the output signal of said first logic circuit as an input thereof
• a fourth flip-flop circuit using the output signal of said second logic circuit as an input thereof;
• and
• a third logic circuit whose output changes in accordance with a normal change of the output signals of said third and fourth flip-flop circuits;
• wherein said first and second flip-flop circuits enter a data-through state in the first state of said clock signal and a data-hold state in the second state of said clock signal, and said third and fourth flip-flop circuits enter the data-hold state in the first state of said clock signal and the data-through state in the second state of said clock signal.

A semiconductor device comprising:

• an internal circuit having at least three flip-flop circuits for inputting the same signal, and
• a majority logic circuit for outputting a signal in accordance with a logic value of the majority of the outputs of said at least three flip-flop circuits, and constituted by MOS transistors;
• and
• an output circuit for receiving signals from said internal circuit and outputting signals to outside,
• wherein a gate width of said MOS transistors constituting said data hold circuit is smaller than at least a gate width of MOS transistors constituting said output circuit.

A semiconductor device comprising:

• an internal circuit having first and second flip-flop circuits using the same signal as an input, and acquiring input signals on the basis of the same clock signal or mutually different clock signals synchronized with each other;
• first and second logic circuits whose output changes in accordance with a normal change of the output signals of said first and second flip-flop circuits;
• a third flip-flop circuit using the output signal of said first logic circuit as an input thereof;
• a fourth flip-flop circuit using the output signal of said second logic circuit as an input thereof;
• and
• a third logic circuit whose output changes in accordance with a normal change of the output signals of said third and fourth flip-flop circuits;
• wherein said first and second flip-flop circuits enter a data-through state in the first state of said clock signal and a data-hold state in the second state of said clock signal, and said third and fourth flip-flop circuits enter the data-hold state in the first state of said clock signal and the data through state in the second state of said clock signal.