Semiconductor chip and multi-chip module
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsShiro Sakiyama, Jun Kajiwara, Masayoshi Kinoshita
Life of this patent
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Abstract
A bare-chip IP of a multi-chip module and an external device of the multi-chip module are interfaced with each other through a dedicated I/O bare-chip IP. Each of the bare-chip IPs other than the dedicated I/O bare-chip IP is not provided with an interface circuit for connection to the external device, and thus is only required to have a withstand voltage characteristic corresponding to the operating voltage of an internal circuit. As a result, it is only necessary to provide, on the bare-chip IPs, transistors of a few kinds of withstand voltage characteristics.
Claims10
An I/O semiconductor chip provided in a multi-chip module, said multi-chip module includes a plurality of semiconductor chips and a plurality of external terminals, the I/O semiconductor chip comprising an input/output function section including a plurality of input/output circuits that are provided between the plurality of external terminals and the plurality of semiconductor chips, said plurality of semiconductor chips having no direct connection to the plurality of external terminals.
A multi-chip module comprising a plurality of semiconductor chips and a plurality of external terminals, the multi-chip module comprising an I/O semiconductor chip that includes an input/output function section including a plurality of input/output circuits provided between the plurality of semiconductor chips and the plurality of external terminals, said plurality of semiconductor chips having no direct connection to the plurality of external terminals.
A multi-chip module comprising a group of small chips mounted on a large chip that includes a plurality of external terminals, the multi-chip module comprising an I/O semiconductor chip that includes an input/output function section including a plurality of input/output circuits provided between the plurality of external terminals on the large chip and individual ones of the group of small chips, said group of small chips having no direct connection to the plurality of external terminals.
Dependencies are inferred from the claim text.