Thin and heat radiant semiconductor package and method for manufacturing

A packaged semiconductor, comprising:

• a leadframe having a plurality of tie bars, each of said tie bars having a side surface and a bottom surface, said leadframe further having a space for receiving a semiconductor chip;
• a semiconductor chip having a planar upper surface, a perimeter and a bottom surface secured into said space defined by said leadframe;
• a plurality of leads connected to said leadframe, each of said plurality of leads having a side surface, an upper surface, and a bottom surface, each of said plurality of leads further having a half-etched section facing said semiconductor chip;
• a plurality of conductive wires electrically connecting said plurality of leads to said semiconductor chip;
• encapsulant material encapsulating said semiconductor chip, said plurality of conductive wires, and said plurality of leads to form a package body;
• a ground ring having a top surface and a bottom surface, said ground ring being disposed between said plurality of leads and said semiconductor chip;
• wherein said bottom surfaces of said semiconductor chip and said plurality of leads are exposed within said package body, and said top surface of said ground ring and said upper surfaces of said plurality of leads are substantially co-planar.

A packaged semiconductor, comprising:

• a semiconductor chip having a planar upper surface, a perimeter and a bottom surface;
• a plurality of input bond pads on the planar upper surface of the semiconductor chip along the perimeter and electrically connected to said semiconductor chip;
• a plurality of output bond pads on the planar upper surface along the perimeter of said semiconductor chip and electrically connected to said semiconductor chip;
• a leadframe having a plurality of tie bars which each have a side surface and a bottom surface, and a ground ring having an upper surface and a bottom surface;
• a plurality of leads connected to said leadframe, each of said plurality of leads having a side surface, an upper surface, and a bottom surface, said plurality of leads being spaced apart from said perimeter of said semiconductor chip and extending toward said semiconductor chip, each of said leads further having a half-etched section facing said semiconductor chip;
• a plurality of conductive wires electrically connecting said plurality of leads to said semiconductor chip;
• encapsulant material encapsulating said semiconductor chip, said plurality of conductive wires, and said plurality of leads to form a package body;
• a chip paddle connected to said leadframe, said chip paddle having a top surface, a side surface and a bottom surface, said chip paddle being bonded to said bottom surface of said semiconductor chip by an adhesive, said chip paddle further having corners, a perimeter and a half-etched section at a lower edge of said chip paddle along said chip paddle perimeter;
• wherein said upper surfaces of said plurality of leads, said upper surface of said ground ring, and said top surface of said chip paddle are substantially co-planar, and said bottom surfaces of said leads and said bottom surface of said chip paddle are exposed within said package body.

A packaged semiconductor, comprising:

• a semiconductor chip having a planar upper surface, a perimeter and a bottom surface;
• a plurality of input bond pads on the planar upper surface of the semiconductor chip along the perimeter and electrically connected to said semiconductor chip;
• a plurality of output bond pads on the planar upper surface along the perimeter of said semiconductor chip and electrically connected to said semiconductor chip;
• a leadframe having a plurality of tie bars which each have a side surface and a bottom surface, and a ground ring having a bottom surface, said ground ring functioning as a power ring and being electrically connected to said semiconductor chip;
• a plurality of leads connected to said leadframe, each of said plurality of leads having a side surface, an upper surface, and a bottom surface, said plurality of leads being spaced apart from said perimeter of said semiconductor chip and extending towards said semiconductor chip, each of said leads further having a half-etched section facing said semiconductor chip;
• a plurality of conductive wires electrically connecting said plurality of leads to said semiconductor chip;
• encapsulant material encapsulating said semiconductor chip, said plurality of conductive wires, and said plurality of leads to form a package body;
• a chip paddle connected to said leadframe, said chip paddle having a top surface, a side surface and a bottom surface, said chip paddle being bonded to said bottom surface of said semiconductor chip by an adhesive, said chip paddle further having corners, a perimeter and a half-etched section at a lower edge of said chip paddle along said chip paddle perimeter;
• wherein said upper surfaces of said plurality of leads and said top surface of said chip paddle are substantially co-planar, and said bottom surfaces of said leads and said bottom surface of said chip paddle are exposed within said package body.

A packaged semiconductor, comprising:

• a semiconductor chip having a planar upper surface, a perimeter and a bottom surface;
• a plurality of input bond pads on the planar upper surface of the semiconductor chip along the perimeter and electrically connected to said semiconductor chip;
• a plurality of output bond pads on the planar upper surface along the perimeter of said semiconductor chip and electrically connected to said semiconductor chip;
• a leadframe having a plurality of tie bars which each have a side surface and a bottom surface, and a ground ring having a bottom surface;
• a plurality of leads connected to said leadframe, each of said plurality of leads having a side surface, an upper surface, and a bottom surface, said plurality of leads being spaced apart from said perimeter of said semiconductor chip and extending towards said semiconductor chip, each of said leads further having a half-etched section facing said semiconductor chip;
• a plurality of conductive wires electrically connecting said plurality of leads to said semiconductor chip;
• encapsulant material encapsulating said semiconductor chip, said plurality of conductive wires, and said plurality of leads to form a package body;
• a chip paddle connected to said leadframe, said chip paddle having a top surface, a side surface and a bottom surface, said chip paddle being bonded to said bottom surface of said semiconductor chip by an adhesive, said chip paddle further having corners, a perimeter and a half-etched section at a lower edge of said chip paddle along said chip paddle perimeter;
• wherein said bottom surfaces of said leads, said bottom surface of said ground ring and said bottom surface of said chip paddle are exposed within said package body.

A packaged semiconductor, comprising:

• a semiconductor chip having a planar upper surface, a perimeter and a bottom surface;
• a plurality of input bond pads on the planar upper surface of the semiconductor chip along the perimeter and electrically connected to said semiconductor chip;
• a plurality of output bond pads on the planar upper surface along the perimeter of said semiconductor chip and electrically connected to said semiconductor chip;
• a leadframe having a plurality of tie bars which each have a side surface and a bottom surface, and a ground ring having an upper surface and a bottom surface;
• a plurality of leads connected to said leadframe, each of said plurality of leads having a side surface, an upper surface, and a bottom surface, said plurality of leads being spaced apart from said perimeter of said semiconductor chip and extending toward said semiconductor chip, each of said leads further having a half-etched section facing said semiconductor chip;
• a plurality of conductive wires electrically connecting said plurality of leads to said semiconductor chip;
• encapsulant material encapsulating said semiconductor chip, said plurality of conductive wires, and said plurality of leads to form a package body;
• a chip paddle connected to said leadframe, said chip paddle having a top surface, a side surface and a bottom surface, said chip paddle being bonded to said bottom surface of said semiconductor chip by an adhesive, said chip paddle further having corners, a perimeter and a half-etched section at a lower edge of said chip paddle along said chip paddle perimeter;
• wherein said upper surface of said ground ring and said top surface of said chip paddle are substantially co-planar, and the bottom surfaces of said leads are exposed within said package body.

A packaged semiconductor, comprising:

• a semiconductor chip having a planar upper surface, a perimeter and a bottom surface;
• a plurality of input bond pads on the planar upper surface of the semiconductor chip along the perimeter and electrically connected to said semiconductor chip;
• a plurality of output bond pads on the planar upper surface along the perimeter of said semiconductor chip and electrically connected to said semiconductor chip;
• a leadframe having a plurality of tie bars which each have a side surface and a bottom surface, and a ground ring having a bottom surface, said ground ring functioning as a power ring and being electrically connected to said semiconductor chip;
• a plurality of leads connected to said leadframe, each of said plurality of leads having a side surface, an upper surface, and a bottom surface, said plurality of leads being spaced apart from said perimeter of said semiconductor chip and extending towards said semiconductor chip, each of said leads further having a half-etched section facing said semiconductor chip;
• a plurality of conductive wires electrically connecting said plurality of leads to said semiconductor chip;
• encapsulant material encapsulating said semiconductor chip, said plurality of conductive wires, and said plurality of leads to form a package body;
• a chip paddle connected to said leadframe, said chip paddle having a top surface, a side surface and a bottom surface, said chip paddle being bonded to said bottom surface of said semiconductor chip by an adhesive, said chip paddle further having corners, a perimeter and a half-etched section at a lower edge of said chip paddle along said chip paddle perimeter;
• wherein said bottom surfaces of said leads are exposed within said package body.