Power chip scale package
AssigneeFairchild Semiconductor Corporation
InventorsMaria Cristina B. Estacio, Ruben Madrid
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Abstract
A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.
Claims8
A semiconductor device comprising:
- a. a leadframe comprising:
- i. a source pad;
- ii. at least two source lead rails at a periphery of the source pad;
- iii. a gate pad adjacent the source pad and electrically isolated therefrom;
- and
- iv. gate lead rail at a periphery of the gate pad;
- b. a die coupled to the source pad and the gate pad;
- and
- c. a stiffener coupled to the leadframe and electrically isolated therefrom.
A semiconductor device comprising:
- a. a leadframe including a top and a bottom surface and gate and source leads;
- b. a die coupled to the bottom surface such that a surface of the die is coplanar with the gate and source leads;
- and
- c. a stiffener coupled to the top surface and electrically isolated therefrom.
Dependencies are inferred from the claim text.