Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method

A method of arranging a buffer cell on a multi-layer wiring structured semiconductor integrated circuit, comprising:

• forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• forming a wiring path in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at a first arbitrary point in the horizontal direction or the vertical direction without going through the other layer;
• and
• inserting a buffer cell at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein
• the first arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A multi-layer wiring structured semiconductor integrated circuit device containing a buffer cell, comprising:

• a semiconductor area in which a plurality of unit elements are formed;
• a plurality of wiring layers, each of which is wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• a wiring path formed in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at a first arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer;
• and
• a buffer cell inserted at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein
• the first arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A multi-layer wiring method structured semiconductor integrated circuit device containing a buffer cell, comprising:

• a semiconductor area in which a plurality of unit elements are formed;
• a plurality of wiring layers, each of which is wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• a wiring path formed in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at a first arbitrary point in the horizontal direction or the vertical direction without going through the other layer;
• and
• a buffer cell inserted at a second arbitrary point on an 45 degree wiring or 135 degree wiring on said wiring path, which reduces signal propagation delay of a wiring, wherein
• the first arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A method of forming a wiring path on a multi-layer wiring structured semiconductor integrated circuit, comprising:

• forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• forming a wiring path in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein
• said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and
• the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A method of forming a wiring path on a multi-layer wiring structured semiconductor integrated circuit, comprising:

• forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• forming a wiring path in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein
• said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and
• the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A multi-layer wiring structured semiconductor integrated circuit device, comprising:

• a semiconductor area in which a plurality of unit elements are formed;
• a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• a wiring path formed in each wiring layer by bending a horizontal direction wiring or a vertical direction wiring in the wiring layers at an arbitrary point in the 45 degrees direction or the 135 degrees direction without going through the other layer, wherein
• said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and
• the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A multi-layer wiring structured semiconductor integrated circuit device, comprising:

• a semiconductor area in which a plurality of unit elements are formed;
• a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• a wiring path formed in each wiring layer by bending a 45 degrees direction wiring or a 135 degrees direction wiring in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein
• said wiring path detours around an obstruction area defined along 45 degree and 135 degree direction wirings through which a wiring cannot pass, and
• the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A method of forming a clock tree which supplies a clock signal to a synchronizing circuit on a multi-layer wiring structured semiconductor integrated circuit, comprising:

• forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• forming a clock tree by bending a horizontal direction wiring or a vertical direction wiring thereof in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein
• said clock tree controls a clock delay in a end thereof, and
• the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A method of forming a clock tree which supplies a clock signal to a synchronizing circuit on a multi-layer wiring structured semiconductor integrated circuit, comprising:

• forming a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• forming a clock tree by bending a 45 degrees direction wiring or a 135 degrees direction wiring thereof in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein
• said clock tree controls a clock delay in a end thereof, and
• the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A multi-layer wiring structured semiconductor integrated circuit device, comprising:

• a semiconductor area in which a plurality of unit elements are formed;
• a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• a clock tree which supplies a clock signal to a synchronizing circuit by bending a horizontal direction wiring or a vertical direction wiring thereof in the wiring layers at an arbitrary point in 45 degrees direction or 135 degrees direction without going through the other layer, wherein
• said clock tree controls a clock delay in a end thereof, and
• the arbitrary point where the horizontal direction wiring or the vertical direction wiring is to be bent is determined so as to substantially minimize a wiring delay.

A multi-layer wiring structured semiconductor integrated circuit device, comprising:

• a semiconductor area in which a plurality of unit elements are formed;
• a plurality of wiring layers, each of which is to be wired in at least one of a horizontal direction, a vertical direction, and in directions that are 45 degrees and 135 degrees inclined from the horizontal direction in a same wiring layer;
• and
• a clock tree which supplies a clock signal to a synchronizing circuit by bending a 45 degrees direction wiring or a 135 degrees direction wiring thereof in the wiring layers at an arbitrary point in the horizontal direction or the vertical direction without going through the other layer, wherein
• said clock tree controls a clock delay in a end thereof, and
• the arbitrary point where the 45 degree direction wiring or the 135 degree direction wiring is to be bent is determined so as to substantially minimize a wiring delay.